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Digital clock manager
Known as:
DCM
, DFS
, Digital Frequency Synthesizer
A digital clock manager (DCM) is an electronic component available on some FPGAs (notably ones produced by Xilinx). A DCM is useful for manipulating…
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Related topics
Related topics
7 relations
Clock signal
Clock skew
Delay-locked loop
Duty cycle
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Broader (1)
Digital electronics
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2012
2012
A Dither-Less All Digital PLL for Cellular Transmitters
Luca Vercesi
,
Luca Fanori
,
F. Bernardinis
,
A. Liscidini
,
R. Castello
IEEE Journal of Solid-State Circuits
2012
Corpus ID: 28811205
An all-digital frequency synthesizer for cellular transmitter is presented. Low phase-noise is achieved both in-band and out-of…
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2008
2008
A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35-$\mu$m CMOS
A. Bonfanti
,
D. Caro
,
A. D. Grasso
,
S. Pennisi
,
C. Samori
,
A. Strollo
IEEE Journal of Solid-State Circuits
2008
Corpus ID: 30677021
A wideband frequency synthesizer architecture is presented. The proposed topology employs a direct digital frequency synthesizer…
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2006
2006
A direct digital frequency synthesizer with fourth-order phase domain ΔΣ noise shaper and 12-bit current-steering DAC
F. Dai
,
Weining Ni
,
Shi Yin
,
R. Jaeger
Symposium on VLSI Circuits
2006
Corpus ID: 14819607
This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single…
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2004
2004
The Application of DDS in IP Core Design of SPWM Generator
Liang Yi
2004
Corpus ID: 64031685
A novel method for realizing a direct digital frequency synthesizer (DDS of DDFS) is presented in this paper, which is improved…
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2002
2002
Hardware optimized direct digital frequency synthesizer architecture with 60 dBc spectral purity
J. Langlois
,
D. Al-Khalili
IEEE International Symposium on Circuits and…
2002
Corpus ID: 42391903
We introduce a novel sine-output Direct Digital Frequency Synthesizer (DDFS) architecture, optimized for hardware implementation…
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Highly Cited
1999
Highly Cited
1999
Design of low-power ROM-less direct digital frequency synthesizer using nonlinear digital-to-analog converter
S. Mortezapour
,
Edward K. F. Lee
IEEE J. Solid State Circuits
1999
Corpus ID: 62563544
A design technique that uses nonlinear digital-to-analog converter (DAC) for implementing low-power direct digital frequency…
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1999
1999
An 800MHz Quadrature Digital Synthesizer with ECLCompatible Output Drivers in 0.8 m CMOS
V. Kroupa
1999
Corpus ID: 62166831
An 800 MHz quadrature direct digital frequency synthesizer (QDDFS4) chip is presented. The chip synthesizes 12 b sine and cosine…
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1998
1998
VLSI design of a CORDIC-based derotator
Y. Ahn
,
S. Nahm
,
Wonyong Sung
ISCAS '98. Proceedings of the IEEE International…
1998
Corpus ID: 62742409
A derotator VLSI which removes the frequency and phase errors of a received signal in digital receivers was developed using a…
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Highly Cited
1995
Highly Cited
1995
A 2-V, 2-GHz low-power direct digital frequency synthesizer chip set for wireless communication
A. Yamagishi
,
M. Ishikawa
,
T. Tsukahara
,
S. Date
Proceedings of the IEEE Custom Integrated…
1995
Corpus ID: 62314577
A 2-GHz direct digital frequency synthesizer (DDFS) chip-set that operates at the very low supply voltage of 2 V is introduced…
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1978
1978
A New PLL Frequency Synthesis Structure
D. Messerschmitt
IEEE Transactions on Communications
1978
Corpus ID: 17730573
In a PLL frequency synthesizer, the reference and VCO frequencies are divided down to their greatest common divisor frequency…
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