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Truncated Binary Multipliers With Variable Correction and Minimum Mean Square Error
Truncated multipliers compute the n most-significant bits of the n × n bits product. This paper focuses on variable-correction truncated multipliers, where some partial-products are discarded, toExpand
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A novel high-speed sense-amplifier-based flip-flop
A new sense-amplifier-based flip-flop is presented. The output latch of the proposed circuit can be considered as an hybrid solution between the standard NAND-based set/reset latch and the NC-/supExpand
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Dual-tree error compensation for high performance fixed-width multipliers
In this paper, a new error-compensation network for fixed-width multipliers is proposed. The error-compensation block is composed of two summation trees which are optimally chosen in order toExpand
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A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS
Spread spectrum clocking is an effective solution to reduce the electromagnetic interference produced by digital chips, using a clock signal with a frequency that is intentionally swept (frequencyExpand
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Direct digital frequency synthesizers with polynomial hyperfolding technique
A new approach to design the phase to sine mapper of a direct digital frequency synthesizer (DDFS) is presented. The proposed technique uses an optimized polynomial expansion of sine and cosineExpand
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Efficient Logarithmic Converters for Digital Signal Processing Applications
The hardware computation of the logarithm function is required in a multitude of applications. This brief investigates logarithmic converters based on piecewise linear approximations. This briefExpand
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Reducing Lookup-Table Size in Direct Digital Frequency Synthesizers Using Optimized Multipartite Table Method
The use of the multipartite table methods (MTMs) to implement high-performance direct digital frequency synthesizers (DDFSs) is investigated in this paper. A closed-form expressions for theExpand
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An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm
In October 2000 the National Institute of Standards and Technology chose Rijndael algorithm as the new Advanced Encryption Standard (AES). AES finds wide deployment in a huge variety of productsExpand
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High-performance direct digital frequency synthesizers using piecewise-polynomial approximation
  • D. D. Caro, A. Strollo
  • Computer Science
  • IEEE Transactions on Circuits and Systems I…
  • 14 February 2005
This paper presents new techniques to implement direct digital frequency synthesizers (DDFSs) with optimized piecewise-polynomial approximation. DDFS performances with piecewise-polynomialExpand
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New clock-gating techniques for low-power flip-flops
Two novel low power flip-flops are presented in the paper. The proposed flip-flops use new gating techniques that reduce power dissipation deactivating the clock signal. The presented circuitsExpand
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