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- Publications
- Influence

Truncated Binary Multipliers With Variable Correction and Minimum Mean Square Error

- N. Petra, D. D. Caro, V. Garofalo, E. Napoli, A. Strollo
- Mathematics, Computer Science
- IEEE Transactions on Circuits and Systems I…
- 1 June 2010

Truncated multipliers compute the n most-significant bits of the n × n bits product. This paper focuses on variable-correction truncated multipliers, where some partial-products are discarded, to… Expand

A novel high-speed sense-amplifier-based flip-flop

- A. Strollo, D. D. Caro, E. Napoli, N. Petra
- Computer Science
- IEEE Transactions on Very Large Scale Integration…
- 1 November 2005

A new sense-amplifier-based flip-flop is presented. The output latch of the proposed circuit can be considered as an hybrid solution between the standard NAND-based set/reset latch and the NC-/sup… Expand

Dual-tree error compensation for high performance fixed-width multipliers

- A. Strollo, N. Petra, D. D. Caro
- Computer Science, Mathematics
- IEEE Transactions on Circuits and Systems II…
- 15 August 2005

In this paper, a new error-compensation network for fixed-width multipliers is proposed. The error-compensation block is composed of two summation trees which are optimally chosen in order to… Expand

A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS

- D. D. Caro, Carlo Alberto Romani, N. Petra, A. Strollo, C. Parrella
- Computer Science
- IEEE Journal of Solid-State Circuits
- 22 April 2010

Spread spectrum clocking is an effective solution to reduce the electromagnetic interference produced by digital chips, using a clock signal with a frequency that is intentionally swept (frequency… Expand

Direct digital frequency synthesizers with polynomial hyperfolding technique

- D. D. Caro, E. Napoli, A. Strollo
- Computer Science
- IEEE Transactions on Circuits and Systems II…
- 19 July 2004

A new approach to design the phase to sine mapper of a direct digital frequency synthesizer (DDFS) is presented. The proposed technique uses an optimized polynomial expansion of sine and cosine… Expand

Efficient Logarithmic Converters for Digital Signal Processing Applications

- D. D. Caro, N. Petra, A. Strollo
- Mathematics, Computer Science
- IEEE Transactions on Circuits and Systems II…
- 3 October 2011

The hardware computation of the logarithm function is required in a multitude of applications. This brief investigates logarithmic converters based on piecewise linear approximations. This brief… Expand

Reducing Lookup-Table Size in Direct Digital Frequency Synthesizers Using Optimized Multipartite Table Method

- D. D. Caro, N. Petra, A. Strollo
- Computer Science
- IEEE Transactions on Circuits and Systems I…
- 7 February 2008

The use of the multipartite table methods (MTMs) to implement high-performance direct digital frequency synthesizers (DDFSs) is investigated in this paper. A closed-form expressions for the… Expand

An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm

- G. P. Saggese, A. Mazzeo, N. Mazzocca, A. Strollo
- Computer Science
- FPL
- 1 September 2003

In October 2000 the National Institute of Standards and Technology chose Rijndael algorithm as the new Advanced Encryption Standard (AES). AES finds wide deployment in a huge variety of products… Expand

High-performance direct digital frequency synthesizers using piecewise-polynomial approximation

- D. D. Caro, A. Strollo
- Computer Science
- IEEE Transactions on Circuits and Systems I…
- 14 February 2005

This paper presents new techniques to implement direct digital frequency synthesizers (DDFSs) with optimized piecewise-polynomial approximation. DDFS performances with piecewise-polynomial… Expand

New clock-gating techniques for low-power flip-flops

- A. Strollo, E. Napoli, D. D. Caro
- Biology, Computer Science
- ISLPED'00: Proceedings of the International…
- 1 August 2000

Two novel low power flip-flops are presented in the paper. The proposed flip-flops use new gating techniques that reduce power dissipation deactivating the clock signal. The presented circuits… Expand