A Dither-Less All Digital PLL for Cellular Transmitters

@article{Vercesi2012ADA,
  title={A Dither-Less All Digital PLL for Cellular Transmitters},
  author={Luca Vercesi and Luca Fanori and Fernando De Bernardinis and Antonio Liscidini and Rinaldo Castello},
  journal={IEEE Journal of Solid-State Circuits},
  year={2012},
  volume={47},
  pages={1908-1920}
}
An all-digital frequency synthesizer for cellular transmitter is presented. Low phase-noise is achieved both in-band and out-of-band exploiting a 2-dimensional Vernier time-to-digital converter and a dither-less digitally controlled oscillator. These building blocks heavily rely on digital calibration techniques to precisely and efficiently implement two-point modulation and spur cancellation in the presence of implementation impairments. The presented prototype shows an in-band phase noise of… CONTINUE READING
Highly Cited
This paper has 41 citations. REVIEW CITATIONS

Citations

Publications citing this paper.
Showing 1-10 of 30 extracted citations

A 28-nm CMOS 40-GHz high-resolution digitally controlled oscillator for automotive radar applications

2017 IEEE 17th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) • 2017

Design Methodology for Phase-Locked Loops Using Binary (Bang-Bang) Phase Detectors

IEEE Transactions on Circuits and Systems I: Regular Papers • 2017

References

Publications referenced by this paper.
Showing 1-10 of 32 references

All-Digital Frequency Synthesizer in Deep-Submicron CMOS

R. B. Staszewski, P. T. Balsara
New York: Wiley, • 2006
View 4 Excerpts
Highly Influenced

A fast-frequency-switching PLL synthesizer LSI with a numerical phase comparator

M. Kokubo
IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig., Feb. 1995, pp. 260–260. • 1995
View 4 Excerpts
Highly Influenced

A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping

IEEE Journal of Solid-State Circuits • 2009
View 5 Excerpts
Highly Influenced

A 2.9-to-4.0 GHz fractional-N digital PLL with bangbang phase detector and 560 fsrms integrated jitter at 4.5 mW power

D. Tasca
IEEE ISSCC Dig., 2011, p. 88. • 2011

A 5.3GHz digital-to-time-converter-based fractional-N all-digital PLL

2011 IEEE International Solid-State Circuits Conference • 2011

Similar Papers

Loading similar papers…