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DLX
Known as:
DLX (disambiguation)
, WinDLX
The DLX (pronounced "Deluxe") is a RISC processor architecture designed by John L. Hennessy and David A. Patterson, the principal designers of the…
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Related topics
Related topics
19 relations
Arithmetic logic unit
Berkeley RISC
Central processing unit
Classic RISC pipeline
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2008
2008
DLX HOTOKADA: A design and implementation of a 32-bit dual core capable DLX microprocessor with single level cache
Darryl Aldrin M. Dioquino
,
Katrina Joy S. Rosario
,
Homer F. Supe
,
J. V. Zarsuela
,
A. Ballesil
,
J. Reyes
15th IEEE International Conference on Electronics…
2008
Corpus ID: 1441658
Data access in main memory units can be sufficient for processors but due to demands for faster computers nowadays…
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2007
2007
VLIW-DLX simulator for educational purposes
M. Becvár
,
Stanislav Kahánek
Workshop On Computer Architecture Education
2007
Corpus ID: 356845
VLIW-DLX is graphical simulator of simple VLIW processor. It is targeted to be used in undergraduate computer architecture…
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2006
2006
Formal Modelling and Verification of an Asynchronous DLX Pipeline
H. Kapoor
IEEE International Conference on Software…
2006
Corpus ID: 17735945
A five stage pipeline of an asynchronous DLX processor is modelled and its control flow is verified. The model is built using an…
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Review
2006
Review
2006
Comments on the genetic control of forebrain development
J. Rubenstein
Clinical Neuroscience Research
2006
Corpus ID: 53205154
2004
2004
Control dlx 3 b and dlx 4 b function in the development of Rohon-Beard sensory neurons and trigeminal placode in the zebrafish neurula
T. Kaji
,
K. Artinger
2004
Corpus ID: 30305729
Rohon-Beard sensory neurons, neural crest cells, and sensory placodes can be distinguished at the boundary of the embryonic…
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2003
2003
Towards Automatic Validation of Dynamic Behavior in Pipelined Processor Specifications
P. Mishra
,
N. Dutt
,
H. Tomiyama
Design automation for embedded systems
2003
Corpus ID: 21037988
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are…
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2002
2002
Automatic modeling and validation of pipeline specifications driven by an architecture description language [SoC]
P. Mishra
,
H. Tomiyama
,
Ashok Halambi
,
P. Grun
,
N. Dutt
,
A. Nicolau
Proceedings of ASP-DAC/VLSI Design . 7th Asia and…
2002
Corpus ID: 1456655
Verification is one of the most complex and expensive tasks in the current systems-on-chip (SOC) design process. Many existing…
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2001
2001
Automatic validation of pipeline specifications
P. Mishra
,
N. Dutt
,
A. Nicolau
Sixth IEEE International High-Level Design…
2001
Corpus ID: 36223
Recent approaches on language-driven Design Space Exploration (DSE) use Architectural Description Languages (ADL) to capture the…
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2001
2001
An Object-Oriented Methodology for Modeling the Precise Behavior of Processor Architectures
J. Otero
,
F. Wagner
IEEE/IFIP International Conference on Very Large…
2001
Corpus ID: 12196881
This paper presents SimPL, an object-oriented methodology for modeling processor behavior with precise timing, which may be used…
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2000
2000
HASE DLX Simulation Model
R. Ibbett
IEEE Micro
2000
Corpus ID: 6794471
This DLX architecture model offers a variety of visualization mechanisms. Instructors use HASE both as a demonstration tool and…
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