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DLX

Known as: DLX (disambiguation), WinDLX 
The DLX (pronounced "Deluxe") is a RISC processor architecture designed by John L. Hennessy and David A. Patterson, the principal designers of the… 
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Related topics

Related topics

19 relations
Arithmetic logic unitBerkeley RISCCentral processing unitClassic RISC pipeline

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2009
2009
Social processes, program verification and all that
In a controversial paper (De Millo et al. 1979) at the end of the 1970's, R. A. De Millo, R. J. Lipton and A. J. Perlis argued… 
2007
2007
Formal Device and Programming Model for a Serial Interface
The verification of device drivers is essential for the pervasive verification of an operating system. To show the correctness of… 
Highly Cited
2007
Highly Cited
2007
A Fully-Automated Desynchronization Flow for Synchronous Circuits
Variability is one of the fundamental problems faced by nano-scale electronic circuits and is expected to become even worse as… 
2004
2004
Function-Complete Lookahead in Support of Efficient SAT Search Heuristics
Recent work has shown the value of using propositional SAT solvers, as opposed to pure BDD solvers, for solving many real-world… 
Highly Cited
2000
Highly Cited
2000
Formal verification of superscalar microprocessors with multicycle functional units, exceptions, and branch prediction
We extend the Burch and Dill flushing technique [6] for formal verification of microprocessors to be applicable to designs where… 
2000
2000
HASE DLX Simulation Model
This DLX architecture model offers a variety of visualization mechanisms. Instructors use HASE both as a demonstration tool and… 
1996
1996
Inverting the Abstraction Mapping: A Methodology for Hardware Verification
Abstraction mappings have become a standard approach to verifying the correctness of processors. When used in a straightforward… 
1995
1995
The DLX instruction set architecture handbook
From the Publisher: The definitive source for the DLX instruction set architecture introduced in John L. Hennessy and David A… 
1993
1993
Implementing a Methodology for Formally Verifying RISC Processors in HOL
In this paper a methodology for verifying RISC cores is presented. This methodology is based on a hierarchical model of… 
1989
1989
Cutting disjoint disks by straight lines
Fork>0 letf(k) denote the minimum integerf such that, for any family ofk pairwise disjoint congruent disks in the plane, there is… 
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