P. Mishra

Publications
Influence

Dynamic cache reconfiguration and partitioning for energy optimization in real-time multi-core systems

Weixun Wang, P. Mishra, S. Ranka
Computer Science
48th ACM/EDAC/IEEE Design Automation Conference…
5 June 2011

In this paper, we present a novel energy optimization technique which employs both dynamic reconfiguration of private caches and partitioning of the shared cache for multicore systems with real-time tasks. Expand

Bitmask-Based Code Compression for Embedded Systems

S. Seong, P. Mishra
Computer Science
IEEE Transactions on Computer-Aided Design of…
1 April 2008

We present a novel code-compression technique using bitmasks, which significantly improves the compression efficiency without introducing any decompression penalty. Expand

Efficient trace signal selection using augmentation and ILP techniques

K. Rahmani, P. Mishra, S. Ray
Computer Science
Fifteenth International Symposium on Quality…
3 March 2014

We propose an efficient simulation-based signal selection technique based on Integer-Linear Programming (ILP) to address these bottlenecks. Expand

Efficient Trace Signal Selection for Post Silicon Validation and Debug

K. Basu, P. Mishra
Engineering, Computer Science
24th Internatioal Conference on VLSI Design
2 January 2011

We propose an approach that efficiently selects a set of signals based on total restorability criteria and can restore up to three times more signals than existing methods. Expand

DyPO: Dynamic Pareto-Optimal Configuration Selection for Heterogeneous MpSoCs

U. Gupta, C. Patil, Ganapati Bhat, P. Mishra, Ümit Y. Ogras
Computer Science
ACM Trans. Embed. Comput. Syst.
10 October 2017

We propose a novel methodology that can find the Pareto-optimal configurations at runtime as a function of the workload. Expand

Decoding-Aware Compression of FPGA Bitstreams

X. Qin, Chetan Muthry, P. Mishra
Engineering, Computer Science
IEEE Transactions on Very Large Scale Integration…
1 March 2011

We proposed a decoding-aware compression technique that tries to obtain both best possible compression and fast decompression performance for variable-length coding. Expand

RATS: Restoration-Aware Trace Signal Selection for Post-Silicon Validation

K. Basu, P. Mishra
Computer Science
IEEE Transactions on Very Large Scale Integration…
1 April 2013

We propose a signal selection approach based on total restorability at gate-level, which is computationally more efficient (10 times faster) and can restore up to three times more signals compared to existing methods. Expand

Test Data Compression Using Efficient Bitmask and Dictionary Selection Methods

K. Basu, P. Mishra
Computer Science
IEEE Transactions on Very Large Scale Integration…
1 September 2010

This paper proposes a novel test data compression technique using bitmasks which provides a substantial improvement in the compression efficiency without introducing any additional decompression penalty. Expand

Instruction set compiled simulation: a technique for fast and flexible instruction set simulation

M. Reshadi, P. Mishra, N. Dutt
Computer Science
Proceedings . Design Automation Conference (IEEE…
2 June 2003

This paper presents a novel technique for generation of fast instruction-set simulators that combines the benefit of both compiled and interpretive simulation while maintaining the flexibility of both. Expand

Functional coverage driven test generation for validation of pipelined processors

P. Mishra, N. Dutt
Computer Science
Design, Automation and Test in Europe
7 March 2005

Functional verification of microprocessors is one of the most complex and expensive tasks in the current system-on-chip design process. Expand

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