Skip to search formSkip to main contentSkip to account menu

Classic RISC pipeline

Known as: Pipeline, Risc pipeline 
In the history of computer hardware, some early reduced instruction set computer central processing units (RISC CPUs) used a very similar… 
Wikipedia (opens in a new tab)

Related topics

Related topics

28 relations
Arithmetic logic unitBranch target predictorBubble (computing)CPU cache

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
An Event Extraction System via Neural Networks
In this paper we describe the IIT KGP team’s participation in the Event Extraction task at FIRE 2017. We have developed an event… 
2003
2003
Efficient design and implementation of image processing algorithms on reconfigurable hardware using Handel-C
Efficient Design and Implementation of Image Processing Algorithms on ReconAgurable Hardware using Handel-C by Venkateshwar Rao… 
2003
2003
FPLD implementation of a PN-matched filter correlator
Typical spread-spectrum receivers use a sliding correlator to achieve synchronization with a received direct sequence spread… 
1997
1997
A pipelined architecture algorithm for image compression
Summary form only given. The article reports a pipelined architecture that can support on-line compression/decompression of image… 
Highly Cited
1997
Highly Cited
1997
Low-power adaptive filter architectures and their application to 51.84 Mb/s ATM-LAN
We present low-power and high-speed algorithms and architectures for complex adaptive filters. These architectures have been… 
1992
1992
A high-performance pipelined architecture for measurement and monitoring of multiple sensor signals
A high-performance pipelined architecture with hardware sharing for measurement and monitoring of signals generated by sensors… 
1992
1992
A binary logic synthesis approach to the bit-level implementation of generalized rank-order filters
  • Q. GuM. Swamy
  • [Proceedings] IEEE International Symposium on…
  • 1992
  • Corpus ID: 60446417
A binary logic synthesis approach is presented for the bit-level implementation of generalized rank-order filters. It is shown… 
1990
1990
A pipelined architecture for on-line low-level vision
The concept of online processing is presented as an effective approach to overcome the data distribution overhead in parallel… 
1989
1989
A pipelined architecture for logic programming with a complex but single-cycle instruction set
  • J. W. Mills
  • [Proceedings ] IEEE International Workshop on…
  • 1989
  • Corpus ID: 12133539
An architecture that executes logic programs using fewer instruction cycles than hardware implementations of the Warren Abstract… 
1987
1987
A parameterized VLSI video-rate histogram processor
A real-time video rate histogram processor has been designed, fabricated and tested. A pipelined architecture was chosen to… 
By clicking accept or continuing to use the site, you agree to the terms outlined in our Privacy Policy (opens in a new tab), Terms of Service (opens in a new tab), and Dataset License (opens in a new tab)