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Classic RISC pipeline

Known as: Pipeline, Risc pipeline 
In the history of computer hardware, some early reduced instruction set computer central processing units (RISC CPUs) used a very similar… 
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Related topics

Related topics

28 relations
Arithmetic logic unitBranch target predictorBubble (computing)CPU cache

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
An Event Extraction System via Neural Networks
In this paper we describe the IIT KGP team’s participation in the Event Extraction task at FIRE 2017. We have developed an event… 
2012
2012
Automatic generation of locally controlled arithmetic unit via floorplan based partitioning
In the paper a framework for generating a locally controlled arithmetic unit is presented including graph generation from a… 
2010
2010
An FPGA implementation of speech recognition with weighted finite state transducers
In this paper we present a hardware architecture for large vocabulary continuous speech recognition that conducts a search over a… 
2009
2009
Reconfigurable architecture for elementary functions evaluation
A reconfigurable architecture for efficient computation of several elementary functions, in double precision floating-point… 
2007
2007
Efficient multi-value connected component labeling algorithm and its ASIC design
An efficient connected component labeling algorithm for multi-value image is proposed in this paper. The algorithm is simple and… 
2005
2005
A high-throughput two channel discrete wavelet transform architecture for the JPEG2000 standard
The Discrete Wavelet Transform (DWT) is increasingly recognized in image and video compression standards, as indicated by its use… 
2003
2003
FPLD implementation of a PN-matched filter correlator
Typical spread-spectrum receivers use a sliding correlator to achieve synchronization with a received direct sequence spread… 
1997
1997
A pipelined architecture algorithm for image compression
Summary form only given. The article reports a pipelined architecture that can support on-line compression/decompression of image… 
1989
1989
A pipelined architecture for logic programming with a complex but single-cycle instruction set
  • J. W. Mills
  • [Proceedings ] IEEE International Workshop on…
  • 1989
  • Corpus ID: 12133539
An architecture that executes logic programs using fewer instruction cycles than hardware implementations of the Warren Abstract… 
1987
1987
A parameterized VLSI video-rate histogram processor
A real-time video rate histogram processor has been designed, fabricated and tested. A pipelined architecture was chosen to… 
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