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Classic RISC pipeline
Known as:
Pipeline
, Risc pipeline
In the history of computer hardware, some early reduced instruction set computer central processing units (RISC CPUs) used a very similar…
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Related topics
Related topics
28 relations
Arithmetic logic unit
Branch target predictor
Bubble (computing)
CPU cache
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
An Event Extraction System via Neural Networks
Alapan Kuila
,
S. Sarkar
Fire
2017
Corpus ID: 3794372
In this paper we describe the IIT KGP team’s participation in the Event Extraction task at FIRE 2017. We have developed an event…
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2016
2016
Real-Time Route 66: Linking External Data Sources
Zubair Nabi
2016
Corpus ID: 64471285
The time budget for streaming data can be on a millisecond scale. Regardless of latency requirements, the first step is…
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2007
2007
AN FPGAIMPLEMENTATIONOFA HIGHRESOLUTIONPHASE SHIFTBEAMFORMER
R. Ayoubi
2007
Corpus ID: 61920758
Inthis work,animplementation ofahighresolution phaseshift beamformer onFPGA ispresented. This implementation isbased…
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2005
2005
55MS/s 10位元 導管式類比數位轉換器之設計
張正文
2005
Corpus ID: 195926744
Many of the applications nowadays utilize the digital signal processing to resolve the transmitted information like as wireless…
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2003
2003
Efficient design and implementation of image processing algorithms on reconfigurable hardware using Handel-C
Venkateshwar Rao Daggu
2003
Corpus ID: 69481289
Efficient Design and Implementation of Image Processing Algorithms on ReconAgurable Hardware using Handel-C by Venkateshwar Rao…
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2003
2003
A pipelined architecture for ray/B ´ ezier patch intersection computation Une architecture en pipeline pour le calcul de l'intersection de pi ` eces de surfaces de B ´ ezier
R. Lewis
,
Renwei Wang
,
D. Hung
2003
Corpus ID: 124225358
An algorithm for computing ray/Bezier patch intersections is described from a hardware design perspective. This algorithm uses…
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2002
2002
Building Spoken Dialogue Systems for Believable Characters
Johan Bos
,
Tetsushi Oka
2002
Corpus ID: 18072827
Believable characters are defined in the arts as autonomous characters with personality, capable of showing emotion, being self…
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Highly Cited
1997
Highly Cited
1997
Low-power adaptive filter architectures and their application to 51.84 Mb/s ATM-LAN
Naresh R Shanbhag
,
M. Goel
IEEE Transactions on Signal Processing
1997
Corpus ID: 224823
We present low-power and high-speed algorithms and architectures for complex adaptive filters. These architectures have been…
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1992
1992
A high-performance pipelined architecture for measurement and monitoring of multiple sensor signals
H. G. Rotithor
1992
Corpus ID: 62652650
A high-performance pipelined architecture with hardware sharing for measurement and monitoring of signals generated by sensors…
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1987
1987
A parameterized VLSI video-rate histogram processor
B. Richards
,
A. Sherstinsky
,
R. Brodersen
ICASSP '87. IEEE International Conference on…
1987
Corpus ID: 60969542
A real-time video rate histogram processor has been designed, fabricated and tested. A pipelined architecture was chosen to…
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