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Branch target predictor

Known as: Branch target buffer 
In computer architecture, a branch target predictor is the part of a processor that predicts the target of a taken conditional branch or an… 
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Branch predictorClassic RISC pipelineComputer architectureInstruction unit

Papers overview

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2019
2019
Announcing the Final Examination of Jingfei Kong for the degree of Doctor of Philosophy Time & Location: June 18, 2010 at 2:00 PM in HEC 302 Title: ARCHITECTURAL SUPPORT FOR IMPROVING COMPUTER…
  • 2019
  • Corpus ID: 267926103
We propose several methods to improve computer security and privacy from architectural point of view. They provide strong… 
2012
2012
Branch Target Buffer Energy Reduction Through Efficient Multiway Branch Translation Techniques
Branch Target Buffer (BTB) plays an important role for pipelined processors in branch prediction during the execution of loops… 
2012
2012
Energy Saving of Value Prediction by Expanding Branch Target Buffer
2012
2012
Path-Based Target Prediction for File System Prefetching
Prefetching is a well-known technique for mitigating the von Neumann bottleneck. In its most rudimentary form, prefetching… 
2010
2010
Low Power Branch Target Buffer Design Based on Hopping Access: Low Power Branch Target Buffer Design Based on Hopping Access
2010
2010
Energy-aware instruction cache design using small trace cache
An instruction cache consumes a significant amount of energy in modern microprocessors. Therefore energy efficiency as well as… 
2002
2002
Using formal tools to study complex circuits behaviour
We use a formal tool to extract Finite State Machines (FSM) based representations (lists of states and transitions) of sequential… 
2002
2002
Minimizing energy consumption for high-performance processing
Power consumption is becoming an increasingly important constraint in the design of microprocessors. This paper examines the use… 
2002
2002
Block Based Fetch Engine for Superscalar Processors
The implementation of modern high performance computer is increasingly directed toward parallelism in the hardware. However, most… 
1994
1994
파이프라인 프로세서에서 분기페널티를 줄이기 위한 하드웨어 방법
RISC(Reduced Instruction Set Computer…