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Branch target predictor

Known as: Branch target buffer 
In computer architecture, a branch target predictor is the part of a processor that predicts the target of a taken conditional branch or an… Expand
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Papers overview

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Highly Cited
2018
Highly Cited
2018
We present BranchScope - a new side-channel attack where the attacker infers the direction of an arbitrary conditional branch… Expand
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Highly Cited
2016
Highly Cited
2016
Address Space Layout Randomization (ASLR) is a widely-used technique that protects systems against a range of attacks. ASLR works… Expand
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2009
2009
Insights into branch predictor organization and operation can be used in architecture-aware compiler optimizations to improve… Expand
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Highly Cited
2007
Highly Cited
2007
Interpreters designed for efficiency execute a huge number of indirect branches and can spend more than half of the execution… Expand
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Highly Cited
2002
Highly Cited
2002
This paper explores the role of branch predictor organization in power/energy/performance tradeoffs for processor design. We find… Expand
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1997
1997
Execution along mispredicted paths may or may not affect the accuracy of subsequent branch predictions if recovery mechanisms are… Expand
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1995
1995
Compile-time reordering of low level instructions is successful in achieving large increases in performance of programs on fine… Expand
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Highly Cited
1993
Highly Cited
1993
A branch target buffer (BTB) can reduce the performance penalty of branches in pipelined processors by predicting the path of the… Expand
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1991
1991
Achieving high instruction issue rates depends on the ability to dynamically predict branches. We compare two schemes for dynamic… Expand
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1988
1988
Abstract The execution of branch instructions causes a loss of performance on pipelined processors. In this paper a new branch… Expand
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