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Branch target predictor

Known as: Branch target buffer 
In computer architecture, a branch target predictor is the part of a processor that predicts the target of a taken conditional branch or an… 
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Related topics

Related topics

5 relations
Branch predictorClassic RISC pipelineComputer architectureInstruction unit

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2019
2019
Evaluating Software Diversity in Branch Prediction Analyses for static WCET Estimation
Static worst-case execution time analysis enables to obtain guaranteed timing bounds for programs, which is required for safety… 
2014
2014
5.5 Steamroller: An x86-64 core implemented in 28nm bulk CMOS
The AMD two-core x86-64 CPU module, codenamed “Steamroller”, contains 236 million transistors implemented in 28nm high-κ metal… 
2013
2013
Dynamic BTB Resizing for Variable Stages Superscalar Architecture
To extract instruction level parallelism (ILP) and thread level parallelism (TLP), super scalar architecture has become commonly… 
2012
2012
Branch Target Buffer Energy Reduction Through Efficient Multiway Branch Translation Techniques
Branch Target Buffer (BTB) plays an important role for pipelined processors in branch prediction during the execution of loops… 
2011
2011
TAP prediction: Reusing conditional branch predictor for indirect branches with Target Address Pointers
Indirect-branch prediction is becoming more important for modern processors as more programs are written in object-oriented… 
2009
2009
A pipelined double-issue MIPS based processor architecture
This paper explains a new design of a high speed MIPS (Microprocessor without Interlocked Pipelined Stages) based processor with… 
2009
2009
Power-aware branch target prediction using a new BTB architecture
This paper presents two effective methods to reduce power consumption of branch target buffer (BTB): 1) the first method is based… 
2002
2002
Using formal tools to study complex circuits behaviour
We use a formal tool to extract Finite State Machines (FSM) based representations (lists of states and transitions) of sequential… 
1996
1996
Branch-directed and stride-based data cache prefetching
  • Yue LiuD. Kaeli
  • Proceedings International Conference on Computer…
  • 1996
  • Corpus ID: 43144311
Cache memories are commonly used to reduce the performance gap between microprocessor and memory technology. To increase the… 
1988
1988
Designing a branch target buffer for executing branches with zero time cost in a RISC processor
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