Skip to search form
Skip to main content
Skip to account menu
Semantic Scholar
Semantic Scholar's Logo
Search 228,397,761 papers from all fields of science
Search
Sign In
Create Free Account
Branch target predictor
Known as:
Branch target buffer
In computer architecture, a branch target predictor is the part of a processor that predicts the target of a taken conditional branch or an…
Expand
Wikipedia
(opens in a new tab)
Create Alert
Alert
Related topics
Related topics
5 relations
Branch predictor
Classic RISC pipeline
Computer architecture
Instruction unit
Expand
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2019
2019
Evaluating Software Diversity in Branch Prediction Analyses for static WCET Estimation
Joachim Fellmuth
,
Jonas Zell
,
S. Glesner
IEEE International Conference on Embedded and…
2019
Corpus ID: 204701382
Static worst-case execution time analysis enables to obtain guaranteed timing bounds for programs, which is required for safety…
Expand
2014
2014
5.5 Steamroller: An x86-64 core implemented in 28nm bulk CMOS
K. Gillespie
,
Harry R. Fair
,
+6 authors
Kathryn Wilcox
IEEE International Solid-State Circuits…
2014
Corpus ID: 39753581
The AMD two-core x86-64 CPU module, codenamed “Steamroller”, contains 236 million transistors implemented in 28nm high-κ metal…
Expand
2014
2014
Linked instruction caches for enhancing power efficiency of embedded systems
Chang-Jung Ku
,
Ching-Wen Chen
,
An Hsia
,
Chun-Lin Chen
Microprocessors and microsystems
2014
Corpus ID: 1411177
2012
2012
Branch Target Buffer Energy Reduction Through Efficient Multiway Branch Translation Techniques
Sumanta Pyne
,
A. Pal
Journal of Low Power Electronics
2012
Corpus ID: 31418008
Branch Target Buffer (BTB) plays an important role for pipelined processors in branch prediction during the execution of loops…
Expand
2009
2009
A pipelined double-issue MIPS based processor architecture
Labibi Tyson
,
Rd Romas
,
Intan P Siti
,
T. Adiono
International Symposium on Intelligent Signal…
2009
Corpus ID: 18313457
This paper explains a new design of a high speed MIPS (Microprocessor without Interlocked Pipelined Stages) based processor with…
Expand
2009
2009
Power-aware branch target prediction using a new BTB architecture
H. Sadeghi
,
H. Sarbazi-Azad
,
H. Zarandi
IEEE/IFIP International Conference on Very Large…
2009
Corpus ID: 44562444
This paper presents two effective methods to reduce power consumption of branch target buffer (BTB): 1) the first method is based…
Expand
2002
2002
Using formal tools to study complex circuits behaviour
P. Amblard
,
Fabienne Lagnier
,
Michel Lévy
Proceedings Euromicro Symposium on Digital System…
2002
Corpus ID: 9097483
We use a formal tool to extract Finite State Machines (FSM) based representations (lists of states and transitions) of sequential…
Expand
Highly Cited
2000
Highly Cited
2000
A hardware mechanism for dynamic extraction and relayout of program hot spots
M. Merten
,
A. Trick
,
E. Nystrom
,
R. D. Barnes
,
W. Hwu
Proceedings of 27th International Symposium on…
2000
Corpus ID: 13281670
This paper presents a new mechanism for collecting and deploying runtime optimized code. The code-collecting component resides in…
Expand
1996
1996
Branch-directed and stride-based data cache prefetching
Yue Liu
,
D. Kaeli
Proceedings International Conference on Computer…
1996
Corpus ID: 43144311
Cache memories are commonly used to reduce the performance gap between microprocessor and memory technology. To increase the…
Expand
1988
1988
Designing a branch target buffer for executing branches with zero time cost in a RISC processor
J. Cortadella
,
T. Jové
Microprocessing and Microprogramming
1988
Corpus ID: 57141552
By clicking accept or continuing to use the site, you agree to the terms outlined in our
Privacy Policy
(opens in a new tab)
,
Terms of Service
(opens in a new tab)
, and
Dataset License
(opens in a new tab)
ACCEPT & CONTINUE