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Optimal bypass monitor for high performance last-level caches
In the last-level cache, large amounts of blocks have reuse distances greater than the available cache capacity. Cache performance and efficiency can be improved if some subset of these distant reuseExpand
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Loose L 1/2 regularised sparse representation for face recognition
Sparse representation (or sparse coding) has been applied to deal with frontal face recognition. Two representative methods are the sparse representation-based classification (SRC) and theExpand
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An energy-efficient branch prediction technique via global-history noise reduction
Accurate branch prediction can improve processor performance, while reducing energy waste. Though some existing branch predictors have been proved effective, they usually require large amount ofExpand
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TAP prediction: Reusing conditional branch predictor for indirect branches with Target Address Pointers
Indirect-branch prediction is becoming more important for modern processors as more programs are written in object-oriented languages. Previous hardware-based indirect-branch predictors generallyExpand
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Energy-efficient branch prediction with Compiler-guided History Stack
Branch prediction is critical in exploring instruction level parallelism for modern processors. Previous aggressive branch predictors generally require significant amount of hardware storage andExpand
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WHOLE: A low energy I-Cache with separate way history
Set-associative instruction caches achieve low miss rates at the expense of significant energy dissipation. Previous energy-efficient approaches usually suffer from performance degradation andExpand
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An adaptive filtering mechanism for energy efficient data prefetching
As data prefetching is used in embedded processors, it is crucial to reduce the wasted energy for improving the energy efficiency. In this paper, we propose an adaptive prefetch filtering (APF)Expand
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SWIP Prediction: Complexity-Effective Indirect-Branch Prediction Using Pointers
Predicting indirect-branch targets has become a performance bottleneck for many applications. Previous high-performance indirect-branch predictors usually require significant hardware storage orExpand
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Improving inclusive cache performance with two-level eviction priority
Inclusive cache hierarchies are widely adopted in modern processors, since they can simplify the implementation of cache coherence. However, it sacrifices some performance to guarantee inclusion.Expand
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VFCC: A verification framework of cache coherence using parallel simulation
A cache coherence protocol is a vital component of a multiprocessor to maintain the data consistency. In this paper, we proposed VFCC, which is a simulation framework to validate a cache-coherenceExpand
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