Ashok Halambi

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We describe EXPRESSION, a language supporting architectural design space exploration for embedded systems-on-chip (SOC) and automatic generation of a retargetable compiler/simulator toolkit. Key features of our language-driven design methodology include: a mixed behavioral/structural representation supporting a natural specification of the architecture,(More)
| We describe EXPRESSION, a language supporting architectural design space exploration for embedded Systems-on-Chip (SOC) and automatic generation of a retargetable compiler/simulator toolkit. Key features of our language-driven design methodology include: a mixed behavioral/structural representation supporting a natural speci cation of the architecture;(More)
For many embedded applications, program code sizeis a critical design factor. One promising approach forreducing code size is to employ a "dual instruction set",where processor architectures support a normal (usually32 bit) Instruction Set, and a narrow, space-efficient(usually 16 bit) Instruction Set with a limited set of op-codes and access to a limited(More)
We describe V–SAT, a tool for performing design space exploration of System-On-Chip (SOC) architectures. The key components of V–SAT include EXPRESSION, a language for specification of the architecture, SIMPRESS, a simulator generator for analysis/evaluation of the architecture, and the V– SAT GUI front-end for easy specification and detailed analysis. We(More)
Modern Embedded Systems-on-Chips (SOCs) will allow the system designer to customize Intellectual Property (IP) cores ((xed and programmable), together with custom logic and large amounts of embedded memories. As the software content in these emerging embedded SOCs begins to dominate the SOC design process , there is a critical need for support of an(More)
Reservation Tables (RTs) have long been used to detect conflicts between operations that simultaneously access the same architectural resource. Traditionally, these RTs have been specified explicitly by the designer. However, the increasing complexity of modern processors makes the manual specification of RTs cumbersome and error-prone. Furthermore, manual(More)
Advances in semiconductor technology coupled with the increasing availability of soft and hard IP libraries enable embedded system designers to develop Systemson-Chip (SOCs) containing highly customized processors and memories for their speci c applications. However, there is a strong demand for a methodology and tools that support e cient Design Space(More)
Verification is one of the most complex and expensive tasks in the current Systems-on-Chip (SOC) design process. Many existing approaches employ a bottom-up approach to pipeline validation, where the functionality of an existing pipelined processor is, in essence, reverse-engineered from its RT-level implementation. Our approach leverages the system(More)
For many embedded applications, program code size is a critical design factor. One promising approach for reducing code size is to employ a “dual instruction set”, where processor architectures support a normal (usually 32-bit) Instruction Set, and a narrow, space-efficient (usually 16-bit) Instruction Set with a limited set of opcodes and(More)