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CPU multiplier

Known as: Multiplier, Clock doubling, Core/bus ratio 
The internal frequency of microprocessors is usually based on front side bus (FSB) frequency. To calculate internal frequency the CPU multiplies bus… 
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29 relations
AthlonBIOSBus (computing)Clock rate

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
A −242-dB FOM and −71-dBc reference spur ring-VCO-based ultra-low-jitter switched-loop-filter PLL using a fast phase-error correction technique
This work presents an ultra-low jitter, low-reference spur switched-loop-filter (SLF) PLL that uses a fast phase-error correction… 
2016
2016
10.6 A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS
Injection-locked clock multipliers (ILCMs) achieve superior phase noise compared to conventional PLLs [1, 2]. In its simplest… 
2012
2012
ICT as a Change Agent for Higher Education and Society
For India to emerge as a knowledge super power of the world in the shortest possible time it is imperative to convert our… 
2009
2009
FE-I4 ATLAS Pixel Chip Design
FE-I4 is the new ATLAS pixel chip developed for use in upgraded luminosity environments, in the framework of the Insertable B… 
2008
2008
A 0.4 ps-RMS-Jitter 1–3 GHz Ring-Oscillator PLL Using Phase-Noise Preamplification
This paper presents the design and experimental results of a 0.4 ps rms jitter (integrated from 3 kHz to 300 MHz offset at 2.5… 
2005
2005
An estimated open-economy model for the EURO area
We estimate a small open economy DSGE model for the euro area. The household sector optimises an intertemporal utility function… 
2000
2000
A 1.3-cycle lock time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation for "clock on demand"
A 1.3-cycle lock-in time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation is proposed with an array… 
1998
1998
A novel delay-locked loop based CMOS clock multiplier
On-chip clock-rate multiplication is usually achieved using a phase-locked-loop (PLL) circuit. However, integration of such an… 
1988
1988
Generation of high speed CMOS multiplier-accumulators
The authors describe MAGGEN (multiplier-accumulator generator), a technology-independent generator for high-speed CMOS Wallace… 
1978
1978
Parallel Processing Techniques
It is a limiting and perhaps unnatural feature of conventional digital computers with classical von Neumann architectures that… 
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