CPU multiplier

Known as: Multiplier, Clock doubling, Core/bus ratio 
The internal frequency of microprocessors is usually based on front side bus (FSB) frequency. To calculate internal frequency the CPU multiplies bus… (More)
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Topic mentions per year

Topic mentions per year

1979-2017
0102019792017

Papers overview

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2016
2016
An injection-locked clock multiplier (ILCM) is considered to be a promising solution that can generate low-jitter, high-frequency… (More)
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2014
2014
A fast power-on transmitter architecture that enables energy proportional communication for server and mobile platforms is… (More)
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2012
2012
In this paper, we proposed a new architecture of multiplier -andaccumulator (MAC) for high-speed arithmetic and low power… (More)
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Highly Cited
2008
Highly Cited
2008
This paper presents a mostly digital multiplying delay-locked loop (MDLL) architecture that leverages a new time-to-digital… (More)
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2008
2008
This paper presents the design and experimental results of a 0.4 ps rms jitter (integrated from 3 kHz to 300 MHz offset at 2.5… (More)
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Highly Cited
2007
Highly Cited
2007
This paper describes a 6.25-Gb/s 14-mW transceiver in 90-nm CMOS for chip-to-chip applications. The transceiver employs a number… (More)
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2007
2007
This paper describes a 150-400 MHz programmable clock multiplier which uses a recirculating DLL. The clock multiplier uses a… (More)
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Highly Cited
2005
Highly Cited
2005
This paper presents economic models of child development that capture the essence of recent Þndings from the empirical literature… (More)
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2001
2001
This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter… (More)
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1997
1997
The clock frequency for microprocessors can be de-coupled from external logic and memory speed when a phase-locked loop (PLL… (More)
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