Shouli Yan

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—An automatic RC time constant tuning scheme is proposed for high linearity continuous-time-and active RC circuits in a low power consumption environment. Instead of changing the (in-filters), the RC time constant is tuned by discretely varying the integration capacitors to preserve a high linearity. The auto-tuning circuit, consisting of an analog(More)
We present a 5 th-order continuous-time Σ∆ modulator with a hybrid active-passive loop filter consisting of only three amplifiers. The passive integrators save power, and introduce no distortion. The active integrators provide gain and minimize internal noise contributions. A single-bit switched-capacitor DAC is employed as the main feedback DAC for high(More)
—Two novel reversed nested Miller Compensation (RNMC) techniques for low-voltage three-stage amplifiers are proposed in this contribution: Nested Feedforward RNMC (NFRNMC) and Crossed Feedforward RNMC (CFRNMC). Both techniques employ double feedforward paths to remove the right-half-plane zero. The second architecture generates a left-half-plane zero to(More)
The design and modeling of a high performance successive approximation analog-to-digital converter (ADC) using non-binary capacitor array are presented in this paper. A non-binary capacitor array with 20 capacitors is used to design a 16-bit, 1.5 mega samples per second (MSPS) successive approximation ADC. A perceptron learning rule, originally developed(More)
—In this paper, we propose a robust and scalable constant rail to rail CMOS input stage for VLSI cell libraries. The proposed circuit does not rely on the characteristics and particular operation (strong, moderate, and weak inversion) regions of the input transistors and is insensitive to mismatches between p-and n-channel devices. Only standard CMOS(More)