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SUMMARY Low voltage (LV) analog circuit design techniques are addressed in this tutorial. In particular, (i) technology considerations ; (ii) transistor model capable to provide performance and power tradeoffs; (iii) low voltage implementation techniques capable to reduce the power supply requirements, such as bulk-driven, floating-gate, and self-cascode(More)
—This paper presents the design and experimental results of a continuous-time 61 modulator for ADSL applications. Multibit nonreturn-to-zero (NRZ) DAC pulse shaping is used to reduce clock jitter sensitivity. The nonzero excess loop delay problem in conventional continuous-time 61 modulators is solved by our proposed architecture. A prototype third-order(More)
—An automatic RC time constant tuning scheme is proposed for high linearity continuous-time-and active RC circuits in a low power consumption environment. Instead of changing the (in-filters), the RC time constant is tuned by discretely varying the integration capacitors to preserve a high linearity. The auto-tuning circuit, consisting of an analog(More)
We present a 5 th-order continuous-time Σ∆ modulator with a hybrid active-passive loop filter consisting of only three amplifiers. The passive integrators save power, and introduce no distortion. The active integrators provide gain and minimize internal noise contributions. A single-bit switched-capacitor DAC is employed as the main feedback DAC for high(More)
—Two novel reversed nested Miller Compensation (RNMC) techniques for low-voltage three-stage amplifiers are proposed in this contribution: Nested Feedforward RNMC (NFRNMC) and Crossed Feedforward RNMC (CFRNMC). Both techniques employ double feedforward paths to remove the right-half-plane zero. The second architecture generates a left-half-plane zero to(More)
A 10 b 210 MS/s two-step ADC has been implemented in 0.13 mum digital CMOS with an active area of 0.38 mm<sup>2</sup>. Using a proposed capacitor network implemented with small value interconnect capacitors which replaces the resistor ladder/multiplexer in conventional sub-ranging ADCs, and proposed offset canceling comparators, it achieves 74 dB SFDR/55 dB(More)
—In this paper, we propose a robust and scalable constant rail to rail CMOS input stage for VLSI cell libraries. The proposed circuit does not rely on the characteristics and particular operation (strong, moderate, and weak inversion) regions of the input transistors and is insensitive to mismatches between p-and n-channel devices. Only standard CMOS(More)