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Wishbone (computer bus)
Known as:
Wishbone
, Wishbone Bus
The Wishbone Bus is an open source hardware computer bus intended to let the parts of an integrated circuit communicate with each other. The aim is…
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Related topics
Related topics
18 relations
Advanced Microcontroller Bus Architecture
Bus (computing)
Central processing unit
Combinational logic
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2016
2016
FORCE CALCULATION IN UPRIGHT OF A FSAE RACE CAR
Anshul Dhakar
,
R. Ranjan
2016
Corpus ID: 212528884
Forces are generated at the tire contact patch during various maneuvers of the car and transferred to the chassis through the…
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2013
2013
Metglas–Elgiloy bi-layer, stent cell resonators for wireless monitoring of viscosity and mass loading
A. Viswanath
,
S. R. Green
,
J. Kosel
,
Y. Gianchandani
2013
Corpus ID: 18617253
This paper presents the design and evaluation of magnetoelastic sensors intended for wireless monitoring of tissue accumulation…
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2013
2013
Experimental & Finite Element Analysis of Left Side Lower Wishbone Arm of Independent Suspension System
A. Patil
,
V. Patil
2013
Corpus ID: 111528200
The Wishbone control arm is a type of independent suspension used in motor vehicles. The general function of control arms is to…
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2012
2012
Simulation Aspects of a Full-Car ATV Model Semi-Active Suspension
K. Kamalakkannan
,
A. Elayaperumal
,
Sathyaprasad Managlaramam
2012
Corpus ID: 45529234
This paper is concerned with the design, modeling, and simulation and testing procedure of All Terrain Vehicle (ATV) fitted with…
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2012
2012
Memory-mapped I/O over dual port BRAM on FPGA
R. Melo
,
D. M. Caruso
,
S. E. Tropea
VIII Southern Conference on Programmable Logic
2012
Corpus ID: 40721346
Nowadays, Direct Memory Access (DMA) is one of the most used mechanisms for data transfer between a processor and its peripherals…
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2008
2008
Assertion-based verification and on-line testing in Horus
Y. Oddos
,
K. Morin-Allory
,
D. Borrione
International Design and Test Workshop
2008
Corpus ID: 34137126
Horus is a prototype environment for the support of assertion-based design. Formal properties, written in a standard (PSL or SVA…
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2007
2007
Automated Integration and Communication Synthesis of Reconfigurable MPSoC Platform
AbdelHalim Samahi
,
E. Bourennane
NASA/ESA Conference on Adaptive Hardware and…
2007
Corpus ID: 21301667
The communication synthesis is the main problematic in the multiprocessor system-on-chip (MPSoC). To resolve this problem…
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Highly Cited
2007
Highly Cited
2007
Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs
J. Hagemeyer
,
B. Kettelhoit
,
M. Köster
,
Mario Porrmann
International Conference on Engineering of…
2007
Corpus ID: 8603765
Dynamicreconfigurationisapromisingapproachtoenhance the resource efficiency of FPGAs beyond the current possibilities. One of the…
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2005
2005
FPGA-based servo control and three-dimensional dynamic interpolation
K. Oldknow
,
I. Yellowley
IEEE/ASME transactions on mechatronics
2005
Corpus ID: 40646304
The design and implementation of a field-programmable gate array (FPGA)-based controller that employs three-dimensional dynamic…
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2002
2002
Multimedia SoC: a systolic core for embedded DCT evaluation
F. Cariccia
,
P. Cariccia
,
M. Martina
,
A. Molino
,
F. Vacca
Conference Record of the Thirty-Sixth Asilomar…
2002
Corpus ID: 32874417
The growing interest in video standards has fostered many research activities towards efficient transform architectures. Many…
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