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Dynamically reconfigurable hardware allows for implementing systems that can be adapted at run-time according to the needs of the user. This paper presents an architecture that is composed of multiple FPGAs that are connected to an embedded processor. Thus, the architecture is referred to as a Multi-FPGA Clustered Architecture (MFCA). All FPGAs can be(More)
Current FPGAs are heterogeneous partially reconfig-urable architectures, consisting of several resource types, e. g., logic cells and embedded memory. By using partial reconfiguration, arbitrary hardware tasks can be placed and removed at run-time, causing the free FPGA resources to become fragmented over time. This fragmentation can prevent a requested(More)
Partially reconfigurable systems are more and more employed in many application fields, including aerospace. SRAM-based FPGAs represent an extremely interesting hardware platform for this kind of systems, because they offer flexibility as well as processing power. In this paper we report about the ongoing development of a software flow for the generation of(More)
In this paper we present a holistic methodology for automated evaluation of instruction set extensions. We propose a two-stage framework for analyzing the resource efficiency of extending an instruction set. With emphasis to elliptic curve cryptography, several instruction set extensions are implemented to a 32 bit RISC microprocessor and synthesized in a(More)
—In partially reconfigurable architectures, system components can be dynamically loaded and unloaded allowing resources to be shared over time. Dynamic system components are represented by partial reconfiguration (PR) modules. In comparison to a static system, the design of a partially reconfigurable system requires additional design steps, such as(More)
One vision of dynamic hardware reconfiguration is to deliver virtually unlimited hardware resources to a set of hardware tasks implementing arbitrary functions. By using partial reconfiguration, these tasks can be allocated and de-allocated on the reconfigurable architecture while others continue to operate. However, the exact placement of each task can(More)
Dynamic reconfiguration is a promising approach to enhance the resource efficiency of FPGAs beyond the current possibilities. One of the main prerequisites for its implementation is a communication infrastructure that enables data transfer between the hardware modules that are placed on the FPGA at run-time. In this paper we present a new communication(More)