Mario Porrmann

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The feature of partial reconfiguration provided by currently available field programmable gate arrays (FPGAs) makes it possible to change hardware modules while others keep working. The combination of this feature and the high gate capacity enables the integration of dynamic systems that can be adapted to changing demands during runtime. Placing the(More)
Due to the technological progress in the semiconductor industry, more and more components can be integrated on a single die forming a complex System-on-Chip. For enabling an efficient interaction between the various building blocks of today's SoCs, efficient communication structures become more and more essential. In this paper, we present the GigaNoC, a(More)
One vision of dynamic hardware reconfiguration is to deliver virtually unlimited hardware resources to a set of hardware tasks implementing arbitrary functions. By using partial reconfiguration, these tasks can be allocated and de-allocated on the reconfigurable architecture while others continue to operate. However, the exact placement of each task can(More)
Dynamic reconfiguration is a promising approach to enhance the resource efficiency of FPGAs beyond the current possibilities. One of the main prerequisites for its implementation is a communication infrastructure that enables data transfer between the hardware modules that are placed on the FPGA at run-time. In this paper we present a new communication(More)
A hardware accelerator for self-organizing feature maps is presented. We have developed a massively parallel architecture that, on the one hand, allows a resource-efficient implementation of small or medium-sized maps for embedded applications, requiring only small areas of silicon. On the other hand, large maps can be simulated with systems that consist of(More)
Summary form only given. The increasing logic density of current FPGAs (field programmable gate arrays) enables the integration of whole systems on one programmable chip. Some of these FPGAs provide the additional feature of partial dynamic reconfiguration, which permits to change parts of the device while other parts keep working. Combining the features of(More)
In this paper, an implementation of a RISC processor core for SoC designs is presented. We analyze the differences between a prototypical FPGA implementation and standard cell realizations in an 0.6μm and an 0.13μm technology, respectively. The core was developed by using the hardware description language VHDL, which offers the opportunity of adding(More)
A number of FPGA-based rapid prototyping systems for ASIC emulation and hardware acceleration have been developed in recent years. In this paper we present a prototyping system with distinct flexibility and scalability. The designs will be described from an architectural view and measurements of the communication infrastructure will be presented.(More)