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Two's complement
Known as:
Two’s complement
, Two's complement system
, 2s'-complement system
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Two's complement is a mathematical operation on binary numbers, as well as a binary signed number representation based on this operation. Its wide…
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Related topics
Related topics
50 relations
Abstract data type
Adder (electronics)
Adder–subtractor
Arithmetic logic unit
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2011
2011
Reversible adder/subtractor with overflow detector
S. Sultana
,
K. Radecka
Midwest Symposium on Circuits and Systems
2011
Corpus ID: 27496825
This paper presents an efficient way to realize a reversible n-bit subtractor circuit incorporating a reversible full adder based…
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2011
2011
Dynamic Spectrum Management for Multiple-Antenna Cognitive Radio Systems: Designs with Imperfect CSI
Tariq Al-Khasib
,
M. B. Shenouda
,
L. Lampe
IEEE Transactions on Wireless Communications
2011
Corpus ID: 930320
In this paper, we study the problem of resource allocation and optimization for multiple-input multiple-output (MIMO) cognitive…
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Highly Cited
2010
Highly Cited
2010
The crossover from strong to weak chaos for nonlinear waves in disordered systems
T. Laptyeva
,
J. Bodyfelt
,
D. Krimer
,
C. Skokos
,
S. Flach
2010
Corpus ID: 118397177
We observe a crossover from strong to weak chaos in the spatiotemporal evolution of multiple-site excitations within disordered…
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2008
2008
n-LDA: n-Layers Data Aggregation in Sensor Networks
Ioana Rodhe
,
C. Rohner
International Conference on Distributed Computing…
2008
Corpus ID: 92237
We present a protocol for secure data aggregation in wireless sensor networks that offers end-to-end data confidentiality by…
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2007
2007
A High-Performance Low Cost SAD Architecture for Video Coding
Li Yufei
,
Feng Xiubo
,
Wang Qin
IEEE transactions on consumer electronics
2007
Corpus ID: 195721000
This paper presents a high-performance low cost sum of absolute difference (SAD) architecture for motion estimation, which…
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2001
2001
Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic
U. Meyer-Bäse
,
Antonio García
,
F. Taylor
J. VLSI Signal Process.
2001
Corpus ID: 9602631
Field-programmable logic (FPL), often grouped under the popular name field-programmable gate arrays (FPGA), are on the verge of…
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1999
1999
NEDA: a new distributed arithmetic architecture and its application to one dimensional discrete cosine transform
W. Pan
,
A. Shams
,
M. Bayoumi
IEEE Workshop on Signal Processing Systems. SiPS…
1999
Corpus ID: 60646523
Conventional Distributed Arithmetic (DA) is popular in ASIC design and it features on-chip ROM to achieve high speed and…
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1996
1996
A new method for conversion of a 2's complement to canonic signed digit number system and its representation
R. Hashemian
Conference Record of The Thirtieth Asilomar…
1996
Corpus ID: 27322054
A new technique is developed to generate canonic sign digit numbers. The technique is shown to be computationally simple and fast…
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Highly Cited
1989
Highly Cited
1989
Optical Multiplication And Division Using Modified-Signed-Digit Symbolic Substitution
K. Hwang
,
A. Louri
1989
Corpus ID: 2165290
The modified-signed-digit (MSD) number system offers parallel addition and subtraction of any two numbers, with carry propagation…
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1987
1987
On-line scheme for computing rotation factors
M. Ercegovac
,
T. Lang
IEEE Symposium on Computer Arithmetic
1987
Corpus ID: 10883646
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