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Adder (electronics)
Known as:
Adder (electronics
, Half adder
, Carry propagation
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An adder, also called summer, is a digital circuit that performs addition of numbers.In many computers and other kinds of processors, adders are used…
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Related topics
Related topics
50 relations
4000 series
AND gate
AND-OR-Invert
ARM architecture
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2011
2011
Synthesis Techniques for Ternary Quantum Logic
S. B. Mandal
,
A. Chakrabarti
,
S. Sur-Kolay
IEEE International Symposium on Multiple-Valued…
2011
Corpus ID: 2761711
Synthesis of ternary quantum circuits involves basic ternary gates and logic operations in the ternary quantum domain. Works that…
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Highly Cited
2010
Highly Cited
2010
Design of High-speed Modified Booth Multipliers Operating at GHz Ranges
Soojin Kim
,
Kyeongsoon Cho
2010
Corpus ID: 17071803
— This paper describes the pipeline architecture of high-speed modified Booth multipliers. The proposed multiplier circuits are…
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Highly Cited
2009
Highly Cited
2009
Two New Low-Power and High-Performance Full Adders
M. H. Moaiyeri
,
R. F. Mirzaee
,
K. Navi
Journal of Computers
2009
Corpus ID: 6227669
Two new low-power, and high-performance 1-bit Full Adder cells are proposed in this paper. These cells are based on low-power XOR…
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2006
2006
Area-Efficient NEDA Architecture for The 1-D DCT/IDCT
Archana Chidanandan
,
M. Bayoumi
IEEE International Conference on Acoustics Speech…
2006
Corpus ID: 12714138
A new distributed arithmetic has been applied to the 1-D DCT to produce a low power, high throughput architecture. In this paper…
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Review
2001
Review
2001
FFT Acquisition of Periodic, Aperiodic, Puncture, and Overlaid Code Sequences in GPS
Chun Yang
2001
Corpus ID: 44771254
This paper presents a study of FFT-implemented circular correlation and its application to fast direct acquisition of GPS codes…
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1999
1999
Multifunction architectures for RNS processors
Vassilis Paliouras
,
T. Stouraitis
1999
Corpus ID: 7245144
Novel very large-scale integration architectures and a design methodology for adder-based residue number system (RNS) processors…
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1994
1994
Design of high-speed residue-to-binary number system converter based on Chinese Remainder Theorem
S. Piestrak
Proceedings IEEE International Conference on…
1994
Corpus ID: 8360418
The carry-free nature of the residue number system (RNS) has made it attractive for implementing a variety of specialized high…
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1993
1993
A 8.8-ns 54/spl times/54-bit multiplier using new redundant binary architecture
H. Makino
,
Y. Nakase
,
H. Shinohara
Proceedings of IEEE International Conference on…
1993
Corpus ID: 45278663
A new redundant binary (RB) architecture for a high-speed multiplier is presented. In this architecture, a pair of partial…
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1979
1979
Binary convolutional codes for a multiple-access channel (Corresp.)
R. Peterson
,
D. Costello
IEEE Transactions on Information Theory
1979
Corpus ID: 206733608
Binary convolutional (linear) code pairs are investigated for use on the two-user adder channel. Maximum likelihood decoding is…
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1959
1959
Decimal-Binary Conversions in CORDIC
D. Daggett
IRE Transactions on Electronic Computers
1959
Corpus ID: 206673434
A special-purpose, binary computer called CORDIC (COordinate Rotation DIgital Computer) contains a unique arithmetic unit…
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