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Adder–subtractor
Known as:
Adder-subtracter
, Adder-subtractor
In digital circuits, an adder–subtractor is a circuit that is capable of adding or subtracting numbers (in particular, binary).Below is a circuit…
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Related topics
Related topics
12 relations
Adder (electronics)
Adding machine
Arithmetic logic unit
Carry-lookahead adder
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2016
2016
Design and Analysis of Online Arithmetic Operators for Streaming Data in FPGAs
G. Joseph
2016
Corpus ID: 29793273
Online addition and multiplication of streaming data is of prime importance in real time processing of digital signals.The choice…
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2015
2015
Design of a Power efficient Reversible Adder/Subtractor
S. C. Goel
2015
Corpus ID: 212502394
— Quantum Computing has emerged as a futuristic form of computing using reversible logic as its basis. Apart from quantum…
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2013
2013
Design low power 10T full adder using process and circuit techniques
S. Mishra
,
S. S. Tomar
,
S. Akashe
International Symposium on Combinatorial…
2013
Corpus ID: 15012291
In this paper we introduced 10T one-bit full adders, including the most motivating of those are analyzed and compared for speed…
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2013
2013
Design of Ripple Borrow Subtractor using different logic techniques
M. Padmaja
,
S. Anusha
2013
Corpus ID: 4685183
Power dissipation has become an overriding concern for VLSI circuits and it may come to dominate the total chip power consumption…
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2012
2012
All optical integrated full adder-subtractor and demultiplexer using SOA-based Mach- Zehnder interferometer
Sanmukh Kaur
2012
Corpus ID: 17056492
By exploiting nonlinear effects in a semiconductor optical amplifier, different functionalities for all-optical digital signal…
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2008
2008
A Novel Low Power, High Speed 14 Transistor CMOS Full Adder Cell with 50% Improvement in Threshold Loss Problem
.. T.Vigneswaran
,
.. B.Mukundhan
,
.. P.SubbaramiReddy
2008
Corpus ID: 835212
Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors…
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2006
2006
VHDL Implementation of the Fast Wavelet Transform
P. Salama
,
M. Rizkalla
,
M. Eckbauer
J. VLSI Signal Process.
2006
Corpus ID: 37028817
In this paper, a VHDL implementation of a decomposition unit based on Mallat's fast Wavelet Transform, which utilizes a two…
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2005
2005
A heuristic approach for multiple restricted multiplication
Nalin Sidahao
,
G. Constantinides
,
P. Cheung
IEEE International Symposium on Circuits and…
2005
Corpus ID: 2918703
This paper introduces a heuristic solution to the multiple restricted multiplication (MRM) optimization problem. MRM refers to a…
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1995
1995
High-Radix Division with Approximate Quotient-Digit Estimation
P. Fenwick
Journal of universal computer science (Online)
1995
Corpus ID: 9861935
High-radix division, developing several quotient bits per clock, is usually limited by the difficulty of generating accurate high…
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1974
1974
Logical design of a negative binary adder-subtracter
G. S. Rao
,
M. N. Rao
,
E. Krishnamurthy
1974
Corpus ID: 61012146
Two different designs for negative binary adder-subtracter are compared. Ono design uses the method of a hybrid-carry—borrow…
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