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Tape-out
Known as:
Taped-out
, Tapeout
, Taped out
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In electronics design, tape-out or tapeout, also known as pattern generation or PG, is the final result of the design process for integrated circuits…
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Related topics
Related topics
19 relations
AMD 10h
Design closure
Electronic design automation
Film recorder
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
Delay Insensitive Ternary CMOS Logic for Secure Hardware
R. S. P. Nair
,
S. Smith
,
J. Di
2015
Corpus ID: 60758221
As digital circuit design continues to evolve due to progress of semiconductor processes well into the sub 100 nm range, clocked…
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2013
2013
Hold time closure for subthreshold circuits using a two-phase, latch based timing method
Yanqing Zhang
,
B. Calhoun
IEEE SOI-3D-Subthreshold Microelectronics…
2013
Corpus ID: 20623659
This paper presents an ultra low power (ULP) solution to hold time closure for subthreshold circuits across PVT variation and…
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2011
2011
Leakage current, active power, and delay analysis of dynamic dual Vt CMOS circuits under P-V-T fluctuations
Jinhui Wang
,
Na Gong
,
L. Hou
,
Xiaohong Peng
,
R. Sridhar
,
Wu-chen Wu
Microelectronics and reliability
2011
Corpus ID: 13995895
2010
2010
A 133 MHz Radiation-Hardened Delay-Locked Loop
R. Sengupta
,
B. Vermeire
,
L. Clark
,
B. Bakkaloglu
IEEE Transactions on Nuclear Science
2010
Corpus ID: 22409165
A radiation hardened by a design delay-locked loop (DLL) architecture for quadrature phase clock generation in a 133 MHz DDR…
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2008
2008
Implementing the scale vector-thread processor
Ronny Krashinsky
,
C. Batten
,
K. Asanović
TODE
2008
Corpus ID: 1824790
The Scale vector-thread processor is a complexity-effective solution for embedded computing which flexibly supports both vector…
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2008
2008
Performance Evaluation of Elastic GALS Interfaces and Network Fabric
Junbok You
,
Yang Xu
,
Hosuk Han
,
K. Stevens
FMGALS@MEMOCODE
2008
Corpus ID: 15229040
Review
2005
Review
2005
Low-power RT-level synthesis techniques: a tutorial
Massoud Pedram
,
A. Abdollahi
2005
Corpus ID: 8966574
Power consumption and power-related issues have become a first-order concern for most designs and loom as fundamental barriers…
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2005
2005
Streamline verification process with formal property verification to meet highly compressed design cycle
Prosenjit Chatterjee
Proceedings - Design Automation Conference
2005
Corpus ID: 817604
In this paper, the author describes a methodology and tool flow for using formal verification effectively to reduce the…
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2004
2004
Guest Editors' Introduction: RTL to GDSII - From Foilware to Standard Practice
D. Hill
,
A. Kahng
IEEE Design & Test of Computers
2004
Corpus ID: 10158037
CHIP IMPLEMENTATION, from a RTL description in a language such as Verilog or VHDL to tapeout in the form of mask tooling data, is…
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Highly Cited
1987
Highly Cited
1987
Design And Test of the 80386
P. Gelsinger
IEEE Design & Test of Computers
1987
Corpus ID: 25137913
A complex design effort, the 80386 was nevertheless one of the company's most successful projects. The work was completed in less…
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