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Design closure
Known as:
Design constraint
Design closure is the process by which a VLSI design is modified from its initial description to meet a growing list of design constraints and…
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Related topics
Related topics
16 relations
Design flow (EDA)
Electronic design automation
Fan-out
Formal equivalence checking
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Broader (1)
Electronic engineering
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Review
2016
Review
2016
Opportunistic Routing Protocols for Wireless Sensor Networks : A
Survey Mounika
,
Chinnaswamy
2016
Corpus ID: 44049773
One of the most discussed topics in Wireless Sensor Network (WSN) is the routing protocol used in the networks. These protocols…
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2011
2011
Study on corollary of seismic base isolation system on buildings with soft storey
S. Islam
,
M. Jameel
,
S. Ahmad
,
M. Z. Jumaat
2011
Corpus ID: 46236046
Soft storey buildings are characterized by having a storey which has a lot of open spaces. This soft storey creates a major weak…
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2011
2011
Multilevel Power Optimization of Pipelined A/D Converters
Jintae Kim
,
S. Limotyrakis
,
C. Yang
IEEE Transactions on Very Large Scale Integration…
2011
Corpus ID: 10406305
Power dissipation of analog and mixed-signal circuits has emerged as a critical design constraint in today's VLSI systems. This…
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2010
2010
A case for lifetime-aware task mapping in embedded chip multiprocessors
Adam S. Hartman
,
D. E. Thomas
,
B. Meyer
International Conference on Hardware/Software…
2010
Corpus ID: 18917524
Temperature-aware design is emerging as a popular approach to addressing a variety of challenges, including system lifetime. In…
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Highly Cited
2005
Highly Cited
2005
Impacts of nonrectangular fin cross section on the electrical characteristics of FinFET
Xusheng Wu
,
P. Chan
,
M. Chan
IEEE Transactions on Electron Devices
2005
Corpus ID: 22290566
The effects of nonrectangular fin cross section of double-gate FinFETs are studied. For a given top-fin width, which is defined…
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Highly Cited
2004
Highly Cited
2004
Global interconnect design in a three-dimensional system-on-a-chip
J. Joyner
,
P. Zarkesh-Ha
,
J. Meindl
IEEE Transactions on Very Large Scale Integration…
2004
Corpus ID: 38262314
A stochastic model for the global net-length distribution of a three-dimensional system-on-a-chip (3D-SoC) is derived. Using the…
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Highly Cited
2004
Highly Cited
2004
Battery-based intrusion detection
G. A. Jacoby
,
IV NathanielJ.Davis
IEEE Global Telecommunications Conference…
2004
Corpus ID: 12720934
This paper proposes an early warning system via a host-based form of intrusion detection that can alert security administrators…
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2000
2000
Modeling and supervisory control of a disassembly automation workcell based on blocking topology
Kok-Meng Lee
,
M. Kuren
IEEE Trans. Robotics Autom.
2000
Corpus ID: 11688510
This paper describes a model for automated disassembly that accounts for workcell interaction and used product constraints. The…
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1996
1996
Formal design constraints
Nils Klarlund
,
Jari Koistinen
,
M. I. Schwartzbach
Conference on Object-Oriented Programming Systems…
1996
Corpus ID: 15808499
Large software systems are often built on system platforms that support or enforce specific characteristics of the source code or…
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1995
1995
Constraint preserving integrators for general nonlinear higher index DAEs
S. Campbell
,
E. Moore
1995
Corpus ID: 15225002
Summary.In the last few years there has been considerable research on numerical methods for differential algebraic equations…
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