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Design closure
Known as:
Design constraint
Design closure is the process by which a VLSI design is modified from its initial description to meet a growing list of design constraints and…
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Related topics
Related topics
16 relations
Design flow (EDA)
Electronic design automation
Fan-out
Formal equivalence checking
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Broader (1)
Electronic engineering
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Review
2016
Review
2016
Opportunistic Routing Protocols for Wireless Sensor Networks : A
Survey Mounika
,
Chinnaswamy
2016
Corpus ID: 44049773
One of the most discussed topics in Wireless Sensor Network (WSN) is the routing protocol used in the networks. These protocols…
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2013
2013
A Hybrid Airfoil Design Method for Icing Wind Tunnel Tests
Gustavo E. C. Fujiwara
,
B. Woodard
,
Brock D. Wiberg
,
Andrew J. Mortonson
,
M. Bragg
2013
Corpus ID: 54531790
.Modern commercial aircraft wings are far too large to be tested full-scale in existing icing wind tunnels and ice accretion…
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2012
2012
Configurable analog routing methodology via technology and design constraint unification
Po-Cheng Pan
,
Hung-Ming Chen
,
Yi-Kan Cheng
,
Jill Liu
,
Wei-Yi Hu
IEEE/ACM International Conference on Computer…
2012
Corpus ID: 12491414
In this paper, we present a novel configurable analog routing methodology for more efficient analog layout automation. By the…
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2011
2011
Multilevel Power Optimization of Pipelined A/D Converters
Jintae Kim
,
S. Limotyrakis
,
C. Yang
IEEE Transactions on Very Large Scale Integration…
2011
Corpus ID: 10406305
Power dissipation of analog and mixed-signal circuits has emerged as a critical design constraint in today's VLSI systems. This…
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2011
2011
Experimental research for robust design of power transmission components
M. Ognjanović
,
Matug Benur
2011
Corpus ID: 122717964
In the future progress of technical systems it is impossible to avoid the power transmission (PT) components. Mechatronical…
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Highly Cited
2004
Highly Cited
2004
Global interconnect design in a three-dimensional system-on-a-chip
J. Joyner
,
P. Zarkesh-Ha
,
J. Meindl
IEEE Transactions on Very Large Scale Integration…
2004
Corpus ID: 38262314
A stochastic model for the global net-length distribution of a three-dimensional system-on-a-chip (3D-SoC) is derived. Using the…
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2004
2004
Temperature-Aware Performance and Power Modeling
W. Liao
,
Lei He
,
Kevin M. Lepak
2004
Corpus ID: 616313
Power has become the primary design constraint for systems ranging from server computers to handhelds. As semiconductor…
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2003
2003
Control, observation and energy regulation of wake flow instabilities
G. Tadmor
,
B. R. Noack
,
+4 authors
M. Morzynski
42nd IEEE International Conference on Decision…
2003
Corpus ID: 60583710
A three-dimensional Galerkin model is used in feedback design to regulate the perturbation kinetic energy in the flow around a…
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1997
1997
Power analysis of a 32-bit RISC microcontroller integrated with a 16-bit DSP
R. Bajwa
,
N. Schumann
,
H. Kojima
Proceedings / International Symposium on Low…
1997
Corpus ID: 2208588
While power consumption has become an important design constraint very few reports of power analysis of processors are available…
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1993
1993
Morphological pyramids for image coding
J. Crespo
,
J. Serra
Other Conferences
1993
Corpus ID: 122671053
This paper presents a method to compute a partition intended to be used in a region-based coding system where the number of…
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