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Design flow (EDA)
Known as:
Design flows (EDA)
Design flows are the explicit combination of electronic design automation tools to accomplish the design of an integrated circuit. Moore's law has…
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18 relations
Alberto Sangiovanni-Vincentelli
Asynchronous system
Clock signal
Design Automation Conference
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Broader (1)
Digital electronics
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2018
Highly Cited
2018
Loihi: A Neuromorphic Manycore Processor with On-Chip Learning
Mike E. Davies
,
N. Srinivasa
,
+20 authors
Hong Wang
IEEE Micro
2018
Corpus ID: 3608458
Loihi is a 60-mm2 chip fabricated in Intels 14-nm process that advances the state-of-the-art modeling of spiking neural networks…
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Highly Cited
2014
Highly Cited
2014
Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies
S. Kvatinsky
,
G. Satat
,
N. Wald
,
E. Friedman
,
A. Kolodny
,
U. Weiser
IEEE Transactions on Very Large Scale Integration…
2014
Corpus ID: 166787
Memristors are novel devices, useful as memory at all hierarchies. These devices can also behave as logic circuits. In this paper…
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Highly Cited
2007
Highly Cited
2007
Low Power Methodology Manual - for System-on-Chip Design
M. Keating
,
D. Flynn
,
R. Aitken
,
Alan Gibbons
,
K. Shi
2007
Corpus ID: 9785799
Tools alone aren't enough to reduce dynamic and leakage power in complex chip designs - a well-planned methodology is needed…
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Highly Cited
2005
Highly Cited
2005
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
D. Bertozzi
,
A. Jalabert
,
+4 authors
G. Micheli
IEEE Transactions on Parallel and Distributed…
2005
Corpus ID: 14653252
The growing complexity of customizable single-chip multiprocessors is requiring communication resources that can only be provided…
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Highly Cited
2005
Highly Cited
2005
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS
S. Mukhopadhyay
,
H. Mahmoodi
,
K. Roy
IEEE Transactions on Computer-Aided Design of…
2005
Corpus ID: 17227481
In this paper, we have analyzed and modeled failure probabilities (access-time failure, read/write failure, and hold failure) of…
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Highly Cited
2004
Highly Cited
2004
A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation
K. Tiri
,
I. Verbauwhede
Proceedings Design, Automation and Test in Europe…
2004
Corpus ID: 52798781
This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable…
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Highly Cited
2003
Highly Cited
2003
Metropolis: An Integrated Electronic System Design Environment
F. Balarin
,
Yosinori Watanabe
,
H. Hsieh
,
L. Lavagno
,
C. Passerone
,
A. Sangiovanni-Vincentelli
Computer
2003
Corpus ID: 206446849
Today, the design chain lacks adequate support, with most system-level designers using a collection of unlinked tools. The…
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Highly Cited
2003
Highly Cited
2003
SPARK: a high-level synthesis framework for applying parallelizing compiler transformations
S. Gupta
,
N. Dutt
,
Rajesh K. Gupta
,
A. Nicolau
16th International Conference on VLSI Design…
2003
Corpus ID: 14799312
This paper presents a modular and extensible high-level synthesis research system, called SPARK, that takes a behavioral…
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Highly Cited
2002
Highly Cited
2002
A network on chip architecture and design methodology
Shashi Kumar
,
A. Jantsch
,
+5 authors
A. Hemani
Proceedings IEEE Computer Society Annual…
2002
Corpus ID: 6599780
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like…
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Highly Cited
2000
Highly Cited
2000
Design issues for Dynamic Voltage Scaling
T. Burd
,
R. Brodersen
ISLPED'00: Proceedings of the International…
2000
Corpus ID: 11954051
Processors in portable electronic devices generally have a computational load which has time-varying performance requirements…
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