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Design flow (EDA)
Known as:
Design flows (EDA)
Design flows are the explicit combination of electronic design automation tools to accomplish the design of an integrated circuit. Moore's law has…
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18 relations
Alberto Sangiovanni-Vincentelli
Asynchronous system
Clock signal
Design Automation Conference
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Broader (1)
Digital electronics
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2014
2014
A Metaheuristic Scheduler for Time Division Multiplexed Networks-on-Chip
R. B. Sorensen
,
J. Sparsø
,
Mark Ruvald Pedersen
,
J. Hojgaard
IEEE International Symposium on Object/Component…
2014
Corpus ID: 16028403
This paper presents a metaheuristic scheduler for inter-processor communication in multi-processor platforms using time division…
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2011
2011
A Multi-Granularity Power Modeling Methodology for Embedded Processors
Young-Hwan Park
,
S. Pasricha
,
F. Kurdahi
,
N. Dutt
IEEE Transactions on Very Large Scale Integration…
2011
Corpus ID: 6849825
With power becoming a major constraint for multiprocessor embedded systems, it is becoming important for designers to…
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2011
2011
Automated Resource-Aware Floorplanning of Reconfigurable Areas in Partially-Reconfigurable FPGA Systems
C. Bolchini
,
A. Miele
,
C. Sandionigi
International Conference on Field-Programmable…
2011
Corpus ID: 2424750
The floor planning activity is a key step in the design of systems on FPGAs, but the approaches available today rarely consider…
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Highly Cited
2010
Highly Cited
2010
Post-placement power optimization with multi-bit flip-flops
Yao-Tsung Chang
,
Chih-Cheng Hsu
,
Mark Po-Hung Lin
,
Yu-Wen Tsai
,
Sheng-Fong Chen
IEEE/ACM International Conference on Computer…
2010
Corpus ID: 47412997
Optimization for power is always one of the most important design objectives in modern nanometer IC design. Recent studies have…
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2010
2010
Design of High-Throughput Fully Parallel LDPC Decoders Based on Wire Partitioning
N. Onizawa
,
T. Hanyu
,
V. Gaudet
IEEE Transactions on Very Large Scale Integration…
2010
Corpus ID: 33201316
We present a method to design high-throughput fully parallel low-density parity-check (LDPC) decoders. With our method, a decoder…
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2010
2010
An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores
B. Krill
,
Afandi Ahmad
,
A. Amira
,
H. Rabah
Signal processing. Image communication
2010
Corpus ID: 41143688
Highly Cited
2006
Highly Cited
2006
A design flow for configurable embedded processors based on optimized instruction set extension synthesis
R. Leupers
,
K. Karuri
,
S. Kraemer
,
Manish Pandey
Proceedings of the Design Automation & Test in…
2006
Corpus ID: 7572790
Design tools for application specific instruction set processors (ASIPs) are an important discipline in systems-level design for…
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2006
2006
NoC monitoring: impact on the design flow
C. Ciordas
,
K. Goossens
,
A. Radulescu
,
T. Basten
IEEE International Symposium on Circuits and…
2006
Corpus ID: 10114302
Networks-on-chip (NoCs) are a scalable interconnects solution to large scale multiprocessor systems on chip and are rapidly…
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2004
2004
PyGen: a MATLAB/Simulink based tool for synthesizing parameterized and energy efficient designs using FPGAs
J. Ou
,
V. Prasanna
12th Annual IEEE Symposium on Field-Programmable…
2004
Corpus ID: 401408
System level tools based on MATLAB/Simulink are becoming popular for designing applications using FPGAs. In these tools…
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2001
2001
Managing dynamic reconfiguration overhead in systems-on-a-chip design using reconfigurable datapaths and optimized interconnection networks
Zhining Huang
,
S. Malik
Proceedings Design, Automation and Test in Europe…
2001
Corpus ID: 1194975
This research examines the role of dynamically reconfigurable logic in systems-on-a-chip (SoC) design. Specifically we study the…
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