Skip to search form
Skip to main content
Skip to account menu
Semantic Scholar
Semantic Scholar's Logo
Search 230,875,567 papers from all fields of science
Search
Sign In
Create Free Account
Design Automation Conference
Known as:
DAC
, Marie Pistilli
, Pat Pistilli
The Design Automation Conference, or DAC, is an annual event, a combination of a technical conference and a trade show, both specializing in…
Expand
Wikipedia
(opens in a new tab)
Create Alert
Alert
Related topics
Related topics
13 relations
Asia and South Pacific Design Automation Conference
Asynchronous system
Computer-automated design
Design Automation and Test in Europe
Expand
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2013
2013
Skew-bounded low swing clock tree optimization
Can Sitik
,
B. Taskin
ACM Great Lakes Symposium on VLSI
2013
Corpus ID: 2805907
This paper introduces a methodology that optimizes the performance of a low swing clock tree under a skew bound. Low-swing clock…
Expand
2013
2013
Incorporating the impacts of workload-dependent runtime variations into timing analysis
F. Firouzi
,
S. Kiamehr
,
M. Tahoori
,
S. Nassif
Design, Automation and Test in Europe
2013
Corpus ID: 11580427
In the nanometer era, runtime variations due to workload dependent voltage and temperature variations as well as transistor aging…
Expand
2005
2005
A novel algorithm for testing crosstalk induced delay faults in VLSI circuits
Aniket
,
Ravishankar Arunachalam
18th International Conference on VLSI Design held…
2005
Corpus ID: 5753006
Crosstalk between adjacent lines can significantly affect the propagation delay of signals in deep-submicron (DSM) circuits. When…
Expand
2004
2004
Mixed synchronous/asynchronous state memory for low power FSM design
C. Cao
,
B. Oelmann
Euromicro Symposium on Digital System Design…
2004
Corpus ID: 393845
Finite state machine (FSM) partitioning proves effective for power optimization. In this paper we propose a design model based on…
Expand
2003
2003
Low power operating system for heterogeneous wireless communication system
Suet-Fei Li
,
R. A. Sutton
,
J. Rabaey
2003
Corpus ID: 10158328
Operating systems in embedded wireless communication increasingly must satisfy a tight set of constraints, such as power and real…
Expand
Highly Cited
2002
Highly Cited
2002
Embedded memory test and repair: infrastructure IP for SOC yield
Y. Zorian
Proceedings. International Test Conference
2002
Corpus ID: 25951499
Today's system-on-chip typically embeds memory IP cores with very large aggregate bit count per SoC. This trend requires using…
Expand
2002
2002
An Integrated Heuristic Approach to Power-Aware Real-Time Scheduling
Pedro Mejía-Alvarez
,
E. Levner
,
D. Mossé
Power-Aware Computer Systems
2002
Corpus ID: 16287810
We propose to improve battery life in pervasive devices by using multiple processors that trade off computing capacity for…
Expand
1997
1997
Generation of synthetic sequential benchmark circuits
M. Hutton
,
Jonathan Rose
,
D. Corneil
Symposium on Field Programmable Gate Arrays
1997
Corpus ID: 9939843
Programmable logic architectures increase in capacity before commercial circuits are designed for them, yielding a distinct…
Expand
1991
1991
1991 European Design Automation Conference report
N. V. Zanden
SIGD
1991
Corpus ID: 15288710
My primary interest is in logic and high-level synthesis and I found a couple of sessions devoted to these areas. Session 2A…
Expand
1986
1986
Logic synthesis and optimization benchmarks for the 1986 Design Automation Conference
A. Geus
Design Automation Conference
1986
Corpus ID: 2424152
In order to compare logic synthesis and optimization systems, a set of benchmarks has been submitted to a number of authors. The…
Expand
By clicking accept or continuing to use the site, you agree to the terms outlined in our
Privacy Policy
(opens in a new tab)
,
Terms of Service
(opens in a new tab)
, and
Dataset License
(opens in a new tab)
ACCEPT & CONTINUE