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  • Influence
An O-tree representation of non-slicing floorplan and its applications
TLDR
A deterministic floorplanning algorithm utilizing the structure of O-tree is developed with promising performance with average 16% improvement in wire length, and 1% less in dead space over previous CPU-intensive cluster refinement method. Expand
Corner block list: an effective and efficient topological representation of non-slicing floorplan
  • X. Hong, Gang Huang, +4 authors J. Gu
  • Mathematics, Computer Science
  • IEEE/ACM International Conference on Computer…
  • 5 November 2000
TLDR
A corner block list-a new efficient topological representation for non-slicing floorplan is proposed with applications to VLSI floorplan and building block placement and the experimental results demonstrate the algorithm is quite promising. Expand
Ratio cut partitioning for hierarchical designs
  • Y. Wei, Chung-Kuan Cheng
  • Mathematics, Computer Science
  • IEEE Trans. Comput. Aided Des. Integr. Circuits…
  • 1 July 1991
TLDR
It is demonstrated that the ratio cut algorithm can locate the clustering structures in the circuit and a fast heuristic algorithm running in linear time with respect to the number of pins in the circuits is proposed. Expand
Optimal wire sizing and buffer insertion for low power and a generalized delay model
TLDR
This approach represents the first work on buffer insertion to incorporate signal slew into the delay model while guaranteeing optimality and efficiently computes the complete, optimal power-delay trade-off curve for added design flexibility. Expand
Optimal wire sizing and buffer insertion for low power and a generalized delay model
TLDR
Efficient, optimal algorithms for timing optimization by discrete wire sizing and buffer insertion are presented that are able to minimize dynamic power dissipation subject to given timing constraints. Expand
An improved two-way partitioning algorithm with stable performance [VLSI]
  • Chung-Kuan Cheng, Y. Wei
  • Computer Science, Mathematics
  • IEEE Trans. Comput. Aided Des. Integr. Circuits…
  • 1 December 1991
A two-way partitioning algorithm is presented that significantly improves on the highly unstable results typically obtained from the traditional Kernighan-Lin-based algorithms. The algorithm groupsExpand
Floorplanning using a tree representation
TLDR
A deterministic floorplanning algorithm utilizing the structure of O tree is developed with promising performance with average 16% improvement in wire length and 1% less dead space over previous central processing unit (CPU) intensive cluster refinement method. Expand
RePlAce: Advancing Solution Quality and Routability Validation in Global Placement
TLDR
RePlAce is the first work to achieve superior solution quality across all the IS PD-2005, ISPD-2006, MMS, DAC-2012, and ICCAD-2012 benchmark suites with a single global placement engine. Expand
Towards efficient hierarchical designs by ratio cut partitioning
  • Y. Wei, Chung-Kuan Cheng
  • Mathematics, Computer Science
  • IEEE International Conference on Computer-Aided…
  • 5 November 1989
TLDR
It is demonstrated that the ratio cut algorithm can locate the clustering structures in the circuit and as much as 70% improvement over the Kernighan-Lin algorithm in terms of the proposed ratio metric. Expand
An enhanced perturbing algorithm for floorplan design using the O-tree representation
TLDR
This paper reduces the complexity of the deterministic algorithm to O(n2), and experimental results indicate the algorithm maintains the high quality of the Deterministic algorithm at a fraction of the CPU time. Expand
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