• Publications
  • Influence
Interconnect Analysis and Synthesis
From the Publisher: State-of-the-art methods and current perspectives on interconnect The irrepressible march toward smaller and faster integrated circuits has made interconnect a hot topic forExpand
Optimal wire sizing and buffer insertion for low power and a generalized delay model
TLDR
This approach represents the first work on buffer insertion to incorporate signal slew into the delay model while guaranteeing optimality and efficiently computes the complete, optimal power-delay trade-off curve for added design flexibility. Expand
Optimal wire sizing and buffer insertion for low power and a generalized delay model
TLDR
Efficient, optimal algorithms for timing optimization by discrete wire sizing and buffer insertion are presented that are able to minimize dynamic power dissipation subject to given timing constraints. Expand
Mongrel: hybrid techniques for standard cell placement
  • Sungwoo Hur, J. Lillis
  • Engineering, Computer Science
  • IEEE/ACM International Conference on Computer…
  • 5 November 2000
TLDR
Experimental results are presented and are quite promising, demonstrating that there is significant room for improvement in state of the art placement. Expand
Optimal wire sizing and buffer insertion for low power and a generalized delay model
  • J. Lillis, C.-K. Cheng, T.-T.Y. Lin
  • Engineering
  • Proceedings of IEEE International Conference on…
  • 1 December 1995
We present efficient, optimal algorithms for timing optimization by discrete wire sizing and buffer insertion. Our algorithms are able to minimize dynamic power dissipation subject to given timingExpand
New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing
TLDR
This work presents new algorithms for construction of performance driven Rectilinear Steiner Trees under the Elmore delay model that derive an explicit area/delay trade-off curve and achieves this goal by limiting the solution space to the set of topologies induced by a permutation on the sinks of the net. Expand
Optimal and efficient buffer insertion and wire sizing
TLDR
This work presents optimal solutions to the following problems: post-layout buffer insertion, wire-sizing and simultaneous buffer insertion and wire- sizing, and represents the first sub-exponential algorithms for these problems. Expand
Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation
TLDR
This paper provides a novel floorplanning automation framework, integrated in the Xilinx tool chain, which is based on an explicit enumeration of the possible placements of each region, and proposes a genetic algorithm (GA), enhanced with a local search strategy, to automate thefloorplanning activity on the defined direct problem representation. Expand
Floorplanning for Partially-Reconfigurable FPGA Systems via Mixed-Integer Linear Programming
The aim of this paper is to show a novel floorplanner based on Mixed-Integer Linear Programming (MILP), providing a suitable formulation that makes the problem tractable using state-of-the-artExpand
New spectral linear placement and clustering approach
TLDR
This paper proposes an /spl alpha/-order objective function to capture the strengths of both the linear and quadratic objective functions and presents a bottom-up clustering algorithm which iteratively collapses pairs of nodes in a graph using local and global connectivity information. Expand
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