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Fan-out
Known as:
Fan out
, Fanout
In digital electronics, the fan-out of a logic gate output is the number of gate inputs it can feed or connect to. In most designs, logic gates are…
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Related topics
Related topics
25 relations
7400 series
Asynchronous circuit
Boolean circuit
CMOS
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2003
2003
Analysis and design of optimal combinational compactors [logic test]
P. Wohl
,
L. Huisman
Proceedings. 21st VLSI Test Symposium, .
2003
Corpus ID: 21212750
Scan and logic built-in self-test (BIST) are increasingly used to reduce test cost. In these test architectures, many internal…
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2002
2002
Synthesizing datapath circuits for FPGAs with emphasis on area minimization
A. Ye
,
Jonathan Rose
,
D. Lewis
IEEE International Conference on Field…
2002
Corpus ID: 10928292
Large circuits, whether they are arithmetic, digital signal processing, switching, or processors, typically contain a greater…
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2002
2002
Satisfiability models and algorithms for circuit delay computation
L. G. Silva
,
Joao Marques-Silva
,
L. M. Silveira
,
K. Sakallah
TODE
2002
Corpus ID: 9436195
The existence of false paths represents a significant and computationally complex problem in the estimation of the true delay of…
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1996
1996
An exact non-enumerative fault simulator for path-delay faults
Marwan A. Gharaybeh
,
M. Bushnell
,
V. Agrawal
Proceedings International Test Conference . Test…
1996
Corpus ID: 30889608
The present an efficient path-delay fault (PDF) simulator that does not involve enumeration of paths. Our method calculates the…
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1995
1995
Wireless single‐electron logic biased by alternating electric field
A. Korotkov
1995
Corpus ID: 14244823
A new type of ultradense logic based on single‐electron tunneling between conducting islands is proposed. The basic element is a…
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1995
1995
A bootstrapped bipolar CMOS (B2CMOS) Gate for low-voltage applications
S. Embabi
,
A. Bellaouar
,
K. Islam
IEEE J. Solid State Circuits
1995
Corpus ID: 61950344
This paper reports on a BiCMOS logic gate which combines bootstrapping and transient saturation techniques to achieve full swing…
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1994
1994
FPGA partitioning for critical paths
D. Brasen
,
G. Saucier
Proceedings of European Design and Test…
1994
Corpus ID: 10152319
FPGA packages have maximum size constraints much larger than the number of IO pins. The resulting IO bottleneck during circuit…
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1992
1992
Redundancy removal and simplification of combinational circuits
P. R. Menon
,
Hitesh Ahuja
Digest of Papers. IEEE VLSI Test Symposium
1992
Corpus ID: 7763208
Redundancy in combinational circuits is usually identified when faults are found to be undetectable during test generation…
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1979
1979
1 /spl mu/m MOSFET VLSI technology. II. Device designs and characteristics for high-performance logic applications
R. Dennard
,
F. Gaensslen
,
E. J. Walker
,
P. Cook
IEEE Journal of Solid-State Circuits
1979
Corpus ID: 20473692
For pt.I see ibid., vol.SC14, no.2, p.240 (1979). Micrometer-dimension n-channel silicon-gate MOSFETs optimized for high…
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1963
1963
Design of ACP Resistor-Coupled Switching Circuits
D. Chung
,
John A. Palmieri
IBM Journal of Research and Development
1963
Corpus ID: 5286117
Directly coupled logic circuits utilizing silicon transistors have been developed in the Advanced Circuit Program. Silicon…
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