Skip to search form
Skip to main content
Skip to account menu
Semantic Scholar
Semantic Scholar's Logo
Search 232,109,311 papers from all fields of science
Search
Sign In
Create Free Account
Fan-out
Known as:
Fan out
, Fanout
In digital electronics, the fan-out of a logic gate output is the number of gate inputs it can feed or connect to. In most designs, logic gates are…
Expand
Wikipedia
(opens in a new tab)
Create Alert
Alert
Related topics
Related topics
25 relations
7400 series
Asynchronous circuit
Boolean circuit
CMOS
Expand
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
Multicore-Fiber-Enabled WSDM Optical Access Network With Centralized Carrier Delivery and RSOA-Based Adaptive Modulation
Zhenhua Feng
,
Borui Li
,
+13 authors
P. Shum
IEEE Photonics Journal
2015
Corpus ID: 24399857
We proposed and experimentally demonstrated a wavelength-space division multiplexing (WSDM) optical access network architecture…
Expand
Highly Cited
2007
Highly Cited
2007
Accurate and scalable reliability analysis of logic circuits
M. Choudhury
,
K. Mohanram
Design, Automation & Test in Europe Conference…
2007
Corpus ID: 7762737
Reliability of logic circuits is emerging as an important concern that may limit the benefits of continued scaling of process…
Expand
2003
2003
A probabilistic approach to buffer insertion
Vishal Khandelwal
,
A. Davoodi
,
Akash Nanavati
,
Ankur Srivastava
ICCAD-. International Conference on Computer…
2003
Corpus ID: 2324655
This work presents a formal probabilistic approach for solving optimization problems in design automation. Prediction accuracy is…
Expand
Review
2002
Review
2002
On-chip inductance cons and pros
Y. Ismail
IEEE Transactions on Very Large Scale Integration…
2002
Corpus ID: 6560683
Provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and…
Expand
2001
2001
Performance analysis of the simultaneous optical multi-processor exchange bus
C. Katsinis
Parallel Computing
2001
Corpus ID: 16021635
Highly Cited
2000
Highly Cited
2000
Effect of wire delay on the design of prefix adders in deep-submicron technology
Zhijun Huang
,
M. Ercegovac
Conference Record of the Thirty-Fourth Asilomar…
2000
Corpus ID: 14002321
This paper investigates the wire delay effect on the design of prefix adders when the technology moves from 250 nm to 70 nm. The…
Expand
Highly Cited
1996
Highly Cited
1996
Test response compaction using multiplexed parity trees
K. Chakrabarty
,
J. Hayes
IEEE Trans. Comput. Aided Des. Integr. Circuits…
1996
Corpus ID: 17965045
Built-in self-testing requires test response streams from many observation points to be merged (space compaction) and compressed…
Expand
1995
1995
The Validity of Retiming Sequential Circuits
V. Singhal
,
C. Pixley
,
R. Rudell
,
R. Brayton
Design Automation Conference
1995
Corpus ID: 6884828
Retiming has been proposed as an optimization step for sequential circuits represented at the net-list level. Retiming moves the…
Expand
Highly Cited
1993
Highly Cited
1993
The Design of Fault-Tolerant Linear Digital State Variable Systems: Theory and Techniques
A. Chatterjee
,
M. d'Abreu
IEEE Trans. Computers
1993
Corpus ID: 37660596
A theory for error detection in linear digital state variable systems is described. With the aid of a tool called the gain matrix…
Expand
Highly Cited
1980
Highly Cited
1980
Test generation costs analysis and projections
P. Goel
Design Automation Conference
1980
Corpus ID: 38044519
Empirical observations are used to derive analytic formulae for test volumes, parallel fault simulation costs, deductive fault…
Expand
By clicking accept or continuing to use the site, you agree to the terms outlined in our
Privacy Policy
(opens in a new tab)
,
Terms of Service
(opens in a new tab)
, and
Dataset License
(opens in a new tab)
ACCEPT & CONTINUE