Jonathan Rose

Publications184
h-index49
Citations11,918
Highly Influential Citations1,182
Author pages are created from data sourced from our academic publisher partnerships and public sources.

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Architecture and CAD for Deep-Submicron FPGAS
From the Publisher: Architecture and CAD for Deep-Submicron FPGAs addresses several key issues in the design of high-performance FPGA architectures and CAD tools, with particular emphasis on issues… Expand
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VPR: A new packing, placement and routing tool for FPGA research
TLDR
We describe the capabilities of and algorithms used in a ne w FPGA CAD tool, Versatile Place and Route (VPR). Expand
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VTR 7.0: Next Generation Architecture and CAD System for FPGAs
TLDR
VTR can now generate a netlist of the final post-routed circuit which enables detailed simulation of a design for a variety of purposes. Expand
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Measuring the Gap Between FPGAs and ASICs
TLDR
This paper presents experimental measurements of the differences between a 90- nm CMOS field programmable gate array (FPGA) and 90-nm CMOS standard-cell application-specific integrated circuits (ASICs) in terms of logic density, circuit speed, and power consumption for core logic. Expand
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FPGA Architecture: Survey and Challenges
TLDR
Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. Expand
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Measuring the Gap Between FPGAs and ASICs
TLDR
This paper presents experimental measurements of the differences between a 90- nm CMOS field programmable gate array (FPGA) and 90-nm CMOS standard-cell application-specific integrated circuits (ASICs) in terms of logic density, circuit speed, and power consumption for core logic. Expand
  • 563
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  • PDF
The VTR project: architecture and CAD for FPGAs from verilog to routing
TLDR
This paper describes the current status and new release of an ongoing effort to create such a flow - the 'Verilog to Routing' (VTR) project, which is a broad collaboration of researchers. Expand
  • 272
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  • PDF
Timing-driven placement for FPGAs
TLDR
We introduce a new Simulated Annealing-based timing-driven placement algorithm for FPGAs that is able to increase the post-place-and-route speed of 20 MCNC benchmark circuits by 42%. Expand
  • 272
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Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
TLDR
In 1999, most commercial FPGA, like the Altera Flex and Xilinx Virtex FPGAs already had cluster-based logic blocks. Expand
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VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling
TLDR
The VPR toolset has been widely used in FPGA architecture and CAD research, but has not evolved over the past decade. Expand
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