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In shared-memory Chip Multiprocessor (CMP), shared data between different cores must be exchanged through the last-level-shared-cache and cache coherence must be maintained at the same time. As the number of cores increase, the cache coherence wall has become more and more serious. As for the multimedia applications full of streaming-like data, existing(More)
—with the advent of chip multiprocessor (CMP) architecture, programmer must tune the program to the architecture in order to fully utilize the hardware resource. How to parallel program multimedia application in the CMP is a big obstacle. In this paper, we introduce the potential parallelism in the multimedia application and the multi-grain parallelism(More)
Aggressive prefetching may cause much inter-core interference and lead to large performance in shared memory CMP systems. The paper aims at improving system performance and making prefetching effective. We study prefetching-caused inter-core interference of CMP system and propose a Global Prefetcher Aggressiveness Control Scheme (GPACS) to reduce useless(More)
Due to technological parameters and constraints entailed in many-core processor with shared memory systems, it demands new solutions to the cache coherence problem. Directory-based coherence protocols have recently seemed as a possible scalable alternative for CMP designs. Unfortunately, with the number of on-chip cores increasing, many directory design(More)
PURPOSE The aim of this study was to determine whether and how real-time feedback of dynamic foot pressure index (DFPI) could be used to correct toe-walking gait in spastic diplegic children with dynamic equinus. METHODS Thirteen spastic diplegic children with dynamic equinus were asked to wear a monitoring device to record their ambulation during daily(More)
A new DAC circuit with multi-threshold voltage for large panel TFT-CLD source driver is proposed based on its binary-tree structural characters. Through setting different bulk voltages V<sub>B</sub> for different CMOS analog switches, the threshold voltages and the on-resistance of CMOS analog switches are reduced and the signal transmission speed from(More)