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TILE64
Known as:
Tile (disambiguation)
TILE64 is a multicore processor manufactured by Tilera. It consists of a mesh network of 64 "tiles", where each tile houses a general purpose…
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15 relations
Arithmetic logic unit
CPU cache
GNU
GNU C Library
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2013
2013
Direct approaches to exploit many-core architecture in bioinformatics
F. Esteban
,
David Díaz
,
P. Hernández
,
Juan Antonio Caballero
,
G. Dorado
,
S. Gálvez
Future generations computer systems
2013
Corpus ID: 7838000
2013
2013
RISO: Relaxed network-on-chip isolation for cloud processors
Hang Lu
,
Guihai Yan
,
Yinhe Han
,
Binzhang Fu
,
Xiaowei Li
Design Automation Conference
2013
Corpus ID: 14691237
Cloud service providers use workload consolidation technique in many-core cloud processors to optimize system utilization and…
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2011
2011
Parallelizing and optimizing a bioinformatics pairwise sequence alignment algorithm for many-core architecture
David Díaz
,
F. Esteban
,
P. Hernández
,
Juan Antonio Caballero
,
G. Dorado
,
S. Gálvez
Parallel Computing
2011
Corpus ID: 5358630
2011
2011
Floodgate: application-driven flow control in network-on-chip for many-core architectures
Yoshi Shih-Chieh Huang
,
Huang-Yu Liu
,
Yuan-Ying Chang
,
C. King
,
S. Tseng
Network on Chip Architectures
2011
Corpus ID: 2579189
With the prevalence of multi- and many-core architecture, network-on-chip (NoC) is becoming the main paradigm for on-chip…
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2011
2011
Parallel deblocking filter for H.264/AVC implemented on Tile64 platform
C. Yan
,
Feng Dai
,
+4 authors
Yasong Zheng
IEEE International Conference on Multimedia and…
2011
Corpus ID: 14260627
For the purpose of accelerating deblocking filter, which accounts for a significant percentage of H.264/AVC decoding time, some…
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2011
2011
Parallel paradigms and run-time management techniques for many-core architectures: The 2PARMA approach
C. Silvano
,
W. Fornaciari
,
+24 authors
B. Vanthournout
9th IEEE International Conference on Industrial…
2011
Corpus ID: 13823587
The 2PARMA project aims at overcoming the lack of parallel programming models and run-time resource management techniques to…
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Highly Cited
2010
Highly Cited
2010
Processor: A 64-Core SoC with Mesh Interconnect
Shane L. Bell
,
B. Edwards
,
+18 authors
Jon C. Zook
2010
Corpus ID: 29985959
Centralized monolithic processor designs, such as single core and shared bus structures, are not scaling, leading to multicore…
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2010
2010
Parallelization of Motion JPEG Decoder on TILE64 Many-Core Platform
Xuan-Yi Lin
,
Chung-Yu Huang
,
Pei-Man Yang
,
Tai-Wen Lung
,
S. Tseng
,
Yeh-Ching Chung
Methods and Tools of Parallel Programming…
2010
Corpus ID: 693743
The ubiquity of many-core architectures poses challenges to software developers to make scalable software. To parallelize data…
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2009
2009
Research of parallel decoding algrithm in H.264 on TILE64
Guan Hui
,
Wang Hongpeng
2nd IEEE International Conference on Broadband…
2009
Corpus ID: 18801091
Due to the increasing performance requirements of decoding H.264/AVC in High Definition (HD) or larger resolution videos, new…
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2007
2007
The Tile Processor™ architecture: Embedded multicore for networking and digital multimedia
IEEE Hot Chips Symposium
2007
Corpus ID: 44858928
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