Wen-Shan Wang

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A 2.4/5GHz Fully-Integrated Transceiver is implemented in 65nm CMOS technology. To alleviate the cost of external front-end components, the G-mode RF transmit/receive (T/R) switch and a power-efficient linear CMOS PA are fully integrated on-chip. On the other hand, for better performance, only the A-mode PA is integrated on-chip while the external T/R(More)
Two approaches for parallelization of H.264 decoder, data partition and function partition, are realized on a PAC Duo platform, which contains two Parallel Architecture Core Digital Signal Processors (PACDSP's). Eight baseline CIF sequences are decoded and their execution cycles and waiting cycles are examined. There are three roots hindering the(More)
A low-power full-band 802.11abg transceiver in 0.15mum CMOS technology is presented. It shows 4.4/4dB low noise figures in 2.4/5GHz receiver chains. An on-chip PA (power amplifier) delivers 20dBm output P <sub>1dB</sub> -40 to 140degC operation temperature is achieved by sensing technique. On-chip power detector and transmitter to receiver feedback loop(More)
Connected component labeling is an indispensable and one of most time consuming tasks of the applications in computer vision. Many labeling algorithms have been introduced, such as scan plus connection table, scan plus union-find, and contour tracing etc. They would rather use byte data than bit data to represent the binary pixel, which is either 1 or 0,(More)
The number of defect pixels in solid state image sensor grows as the digital imagers continue increasing in image size and pixel density. However, limited number of defect pixels is usually allowed after detection and correction techniques are applied. The defect pixel detection and defect pixel correction are operated separately but the former must employ(More)