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Standard cell
Known as:
Standard
, Cell-based IC
, Library (disambiguation)
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In semiconductor design, standard cell methodology is a method of designing application-specific integrated circuits (ASICs) with mostly digital…
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Related topics
Related topics
36 relations
AND gate
Adder (electronics)
Application-specific integrated circuit
CMOS
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Broader (1)
Electronic design automation
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2010
Highly Cited
2010
SEILA: Soft error immune latch for mitigating multi-node-SEU and local-clock-SET
T. Uemura
,
Y. Tosaka
,
+5 authors
K. Hatanaka
IEEE International Reliability Physics Symposium
2010
Corpus ID: 38987285
We have developed a robust latch for achieving high reliability in LSI. The latch can attenuate multi-node single-event-upset…
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2009
2009
Synchronizer Behavior and Analysis
I. W. Jones
,
Suwen Yang
,
M. Greenstreet
15th IEEE Symposium on Asynchronous Circuits and…
2009
Corpus ID: 27507384
Synchronizer characterization is non-trivial. The exponential response to parameter changes makes this task a challenge, which is…
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Highly Cited
2009
Highly Cited
2009
HDTV1080p H.264/AVC Encoder Chip Design and Performance Analysis
Zhenyu Liu
,
Yang Song
,
+6 authors
T. Ikenaga
IEEE Journal of Solid-State Circuits
2009
Corpus ID: 23482683
A H.264/AVC baseline-profile real-time encoder for HDTV-1080p at 30 fps is proposed in this paper. On the basis of the…
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2009
2009
A Micropower $\Delta\Sigma$-Based Interface ASIC for a Capacitive 3-Axis Micro-Accelerometer
M. Paavola
,
M. Kämäräinen
,
+4 authors
K. Halonen
IEEE Journal of Solid-State Circuits
2009
Corpus ID: 1725066
In this paper, a micropower interface IC for a capacitive 3-axis micro-accelerometer is presented. The IC is implemented in a 0…
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2007
2007
Systematic Simulation-Based Predictive Synthesis of Integrated Optical Interconnect
I. O’Connor
,
F. Tissafi-Drissi
,
+5 authors
D. Stroobandt
IEEE Transactions on Very Large Scale Integration…
2007
Corpus ID: 2548526
Integrated optical interconnect has been identified by the ITRS as a potential solution to overcome predicted interconnect…
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Highly Cited
2003
Highly Cited
2003
Balanced self-checking asynchronous logic for smart card applications
S. Moore
,
Ross J. Anderson
,
R. Mullins
,
G. Taylor
,
J. Fournier
Microprocessors and microsystems
2003
Corpus ID: 2186513
2000
2000
A high-speed MAP architecture with optimized memory size and power consumption
A. Worm
,
H. Lamm
,
N. Wehn
IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS…
2000
Corpus ID: 13826580
This paper presents a novel high-speed maximum a posteriori (MAP) decoder architecture with optimized memory size and power…
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Review
2000
Review
2000
Power Minimisation Techniques for Testing Low Power VLSI Circuits
N. Nicolici
,
B. Al-Hashimi
2000
Corpus ID: 108474829
Power dissipation has become a significant concern in deep submicron VLSI and a substantial amount of research has been conducted…
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1996
1996
High-performance computing using a reconfigurable accelerator
R. Hartenstein
,
J. Becker
,
R. Kress
,
H. Reinig
Concurrency Practice and Experience
1996
Corpus ID: 14613687
AbstractThis paper introduces the MoM-3 as a reconfigurable accelerator for high perform-ance computing at a moderate price. By…
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Highly Cited
1991
Highly Cited
1991
Two Cell Lines from White Sturgeon
R. Hedrick
,
T. McDowell
,
R. Rosemark
,
D. Aronstein
,
C. N. Lannan
1991
Corpus ID: 54890152
Abstract Cell lines were established from spleen and heart tissues of a juvenile white sturgeon Acipenser transmontanus and…
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