Standard cell

Known as: Standard, Cell-based IC, Library (disambiguation) 
In semiconductor design, standard cell methodology is a method of designing application-specific integrated circuits (ASICs) with mostly digital… (More)
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Papers overview

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2011
2011
As the technology scales, the increase of circuit delay over time due to NBTI (negative bias temperature instability) effect is… (More)
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Highly Cited
2008
Highly Cited
2008
Standard cell circuits consist of millions of standard cells, which have to be aligned overlap-free to the rows of the chip… (More)
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Highly Cited
2004
Highly Cited
2004
Side channel attacks can be effectively a ddressed at the circuit level by using dynamic differential logic styles. A key problem… (More)
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Highly Cited
2004
Highly Cited
2004
This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable… (More)
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Highly Cited
2003
Highly Cited
2003
With technology scaling, the trend for high performance integrated circuits is towards ever higher operating frequency, lower… (More)
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Highly Cited
1997
Highly Cited
1997
We present a new top-down quadrisection-based global placer for standard-cell layout. The key contribution is a new general gain… (More)
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Highly Cited
1995
Highly Cited
1995
We present an algorithm for accurately controlling delays during the placement of large standard cell integrated circuits… (More)
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Highly Cited
1995
Highly Cited
1995
Abstruct1-V power supply high-speed low-power digital circuit technology with 0.5-pm multithreshold-voltage CMOS (MTCMOS) is… (More)
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1990
1990
  • Jonathan Rose
  • IEEE Trans. on CAD of Integrated Circuits and…
  • 1990
Combined placement and routing has the potential to achieve better quality automatic layout because the placement optimization… (More)
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Highly Cited
1986
Highly Cited
1986
TimberWolf3.2 is a new standard cell placement and global routing package. The placement and global routing proceed over 3… (More)
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