Skip to search formSkip to main contentSkip to account menu

Standard cell

Known as: Standard, Cell-based IC, Library (disambiguation) 
In semiconductor design, standard cell methodology is a method of designing application-specific integrated circuits (ASICs) with mostly digital… 
Wikipedia (opens in a new tab)

Related topics

Related topics

36 relations
AND gateAdder (electronics)Application-specific integrated circuitCMOS

Broader (1)

Electronic design automation

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2017
Highly Cited
2017
Light-weight wireless power transfer for mid-air charging of drones
Recent developments in high frequency inductive wireless power transfer (WPT) mean that the technology has reached a point where… 
Highly Cited
2012
Highly Cited
2012
Improved CMOS (4; 2) compressor designs for parallel multipliers
Highly Cited
2009
Highly Cited
2009
Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization
Double patterning lithography (DPL) is considered as a most likely solution for 32 nm/22 nm technology. In DPL, the layout… 
Highly Cited
2008
Highly Cited
2008
A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI
An all static CMOS ADPLL fabricated in 65 nm digital CMOS SOI technology has a fully programmable proportional-integral… 
Highly Cited
2008
Highly Cited
2008
DEC ECC design to improve memory reliability in Sub-100nm technologies
  • R. NaseerJ. Draper
  • 15th IEEE International Conference on Electronics…
  • 2008
  • Corpus ID: 10613342
Exacerbated SRAM reliability issues, due to soft errors and increased process variations in sub-100 nm technologies, limit the… 
Highly Cited
2008
Highly Cited
2008
Enhanced Autofocus Algorithm Using Robust Focus Measure and Fuzzy Reasoning
A new passive autofocus algorithm consisting of a robust focus measure for object detection and fuzzy reasoning for target… 
Highly Cited
2007
Highly Cited
2007
A Simple Flip-Flop Circuit for Typical-Case Designs for DFM
The deep submicron (DSM) semiconductor technologies make the worst-case design impossible, since they can not provide design… 
Highly Cited
2005
Highly Cited
2005
A 180-mV subthreshold FFT processor using a minimum energy design methodology
In emerging embedded applications such as wireless sensor networks, the key metric is minimizing energy dissipation rather than… 
Highly Cited
2002
Highly Cited
2002
Point to point GALS interconnect
Reliable, low-latency channel communication between independent clock domains may be achieved using a combination of clock… 
Highly Cited
1993
Highly Cited
1993
Carafe: an inductive fault analysis tool for CMOS VLSI circuits
Traditional fault models for testing CMOS VLSI circuits do not take into account the actual mechanisms that precipitate faults in… 
By clicking accept or continuing to use the site, you agree to the terms outlined in our Privacy Policy (opens in a new tab), Terms of Service (opens in a new tab), and Dataset License (opens in a new tab)