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A synthesizable IP core for DVB-S2 LDPC code decoding
The new standard for digital video broadcast DVB-S2 features low-density parity-check (LDPC) codes as their channel coding scheme. The codes are defined for various code rates with a block size ofExpand
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A Synthesizable IP Core for WIMAX 802.16E LDPC Code Decoding
The upcoming IEEE WiMax 802.16e standard, also referred to as WirelessMAN (2005), is the next step toward very high throughput wireless backbone architectures, supporting up to 500 Mbps. It featuresExpand
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Exploiting expendable process-margins in DRAMs for run-time performance optimization
Manufacturing-time process (P) variations and runtime voltage (V) and temperature (T) variations can affect a DRAM's performance severely. To counter these effects, DRAM vendors provide substantialExpand
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Embedded DRAM Development: Technology, Physical Design, and Application Issues
Embedded DRAM provides advantages from a system point of view, along with many technical challenges. This article presents an overview of circuit, technology, and physical design methodology issuesExpand
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A 477mW NoC-based digital baseband for MIMO 4G SDR
Baseband processing for advanced Telecom applications have to face two contradictory issues [1]. The first one is the flexibility required, with the exploding number of modes for a single protocolExpand
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Low Complexity LDPC Code Decoders for Next Generation Standards
This paper presents the design of low complexity LDPC codes decoders for the upcoming WiFi (IEEE 802.11n), WiMax (IEEE802.16e) and DVB-S2 standards. A complete exploration of the design spaceExpand
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A novel LDPC decoder for DVB-S2 IP
In this paper a programmable Forward Error Correction (FEC) IP for a DVB-S2 receiver is presented. It is composed of a Low-Density Parity Check (LDPC), a Bose-Chaudhuri-Hoquenghem (BCH) decoder, andExpand
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A 2.15GBit/s turbo code decoder for LTE advanced base station applications
The LTE standard [1], will soon be upgraded to LTE advanced, which will add new techniques like multi user MIMO using iterative demodulation, cooperative multi point reception (CoMP) and beam formingExpand
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Reliable on-chip systems in the nano-era: Lessons learnt and future trends
Reliability concerns due to technology scaling have been a major focus of researchers and designers for several technology nodes. Therefore, many new techniques for enhancing and optimizingExpand
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Low complexity stopping criterion for LDPC code decoders
  • F. Kienle, N. Wehn
  • Computer Science
  • IEEE 61st Vehicular Technology Conference
  • 5 December 2005
Low density parity check (LDPC) codes are amongst the most powerful codes known today. They are decoded iteratively by a message-passing algorithm. For this, an inherent stopping criterion exists forExpand
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