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Polysilicon depletion effect
Known as:
Poly Depletion Effect
, Poly depletion
Polysilicon depletion effect is the phenomenon in which unwanted variation of threshold voltage of the MOSFET devices using polysilicon as gate…
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Related topics
Related topics
3 relations
CMOS
Electronic circuit
Gate oxide
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2009
2009
The effect of size on photodiode pinch-off voltage for small pixel CMOS image sensors
Sangsik Park
,
H. Uh
Microelectronics Journal
2009
Corpus ID: 19841799
2009
2009
Modeling of Polysilicon Depletion Effect in Recessed-Channel MOSFETs
Y. Kang
,
Heesang Kim
,
+4 authors
Hyungcheol Shin
IEEE Electron Device Letters
2009
Corpus ID: 36211455
The polysilicon depletion effect is one of the key factors that degrade MOSFETs' performance. In this letter, a polysilicon…
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2007
2007
Compact Gate Capacitance Model with Polysilicon Depletion Effect for MOS Device
H. Abebe
,
H. Morris
,
E. Cumberbatch
,
V. Tyree
2007
Corpus ID: 62675968
The MOS gate capacitance model presented here is determined by directly solving the coupled Poisson equations on the poly and…
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2006
2006
Process Integration Issues with Spike, Flash and Laser Anneal Implementation for 90 and 65 NM Technologies
T. Feudel
,
M. Horstmann
,
+5 authors
J. Kluth
14th IEEE International Conference on Advanced…
2006
Corpus ID: 13934430
With the need to reduce vertical and lateral device dimensions, submelt laser and flash anneal either with or without prior spike…
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2005
2005
A new logic family based on hybrid MOSFET-polysilicon nanowires
S. Ecoffey
,
M. Mazza
,
+5 authors
A. Ionescu
IEEE InternationalElectron Devices Meeting…
2005
Corpus ID: 40211692
A new logic family based on ultra-thin film (10nm) nanograins (5 to 20nm) polysilicon wires (polySiNW) is proposed, validated and…
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1999
1999
Investigation of intrinsic transistor performance of advanced CMOS devices with 2.5 nm NO gate oxides
S. Kubicek
,
W. Henson
,
+7 authors
K. De Meyer
International Electron Devices Meeting…
1999
Corpus ID: 28421134
Optimum device design for high performance applications has been investigated assuming a fixed oxide thickness of 2.5 nm and…
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Highly Cited
1998
Highly Cited
1998
25 nm CMOS design considerations
Y. Taur
,
C. Wann
,
David J. Frank
International Electron Devices Meeting…
1998
Corpus ID: 29825196
This paper explores the limit of bulk (or partially-depleted SOI) CMOS scaling. A feasible design for 25 nm (channel length) CMOS…
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1998
1998
PVD TiN metal gate MOSFETs on bulk silicon and fully depleted silicon-on-insulator (FDSOI) substrates for deep sub-quarter micron CMOS technology
B. Maiti
,
P. Tobin
,
+11 authors
L. La
International Electron Devices Meeting…
1998
Corpus ID: 29801400
We report here for the first time an evaluation of a polysilicon capped physical vapor deposited (PVD) titanium nitride (TiN…
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1996
1996
Accurate doping profile determination using TED/QM models extensible to sub-quarter micron nMOSFETs
P. V. Voorde
,
P. Griffin
,
Z. Yu
,
S. Oh
,
R. Dutton
International Electron Devices Meeting. Technical…
1996
Corpus ID: 34374777
Accurate doping profiles are needed to simulate device characteristics. We use capacitance-voltage curves to interrogate the…
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1981
1981
Ti/W silicide gate technology for self-aligned GaAs MESFET VLSIS
N. Yokoyama
,
T. Ohnishi
,
K. Odani
,
H. Onodera
,
M. Abe
International Electron Devices Meeting
1981
Corpus ID: 21136627
Ti/W mixed metal contacts on GaAs shows instable Schottky diode characteristics with short annealing cycles at temperatures…
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