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Fundamentals of Modern VLSI Devices
Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted asExpand
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Device scaling limits of Si MOSFETs and their application dependencies
This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of theExpand
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Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's
Quantum-mechanical modeling of electron tunneling current from the quantized inversion layer of ultra-thin-oxide (<40 /spl Aring/) nMOSFET's is presented, together with experimental verification. AnExpand
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CMOS scaling into the nanometer regime
Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light ofExpand
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An analytical solution to a double-gate MOSFET with undoped body
A one-dimensional (1-D) analytical solution is derived for an undoped (or lightly-doped) double-gate MOSFET by incorporating only the mobile charge term in Poisson's equation. The solution givesExpand
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A continuous, analytic drain-current model for DG MOSFETs
This letter presents a continuous analytic current-voltage (I-V) model for double-gate (DG) MOSFETs. It is derived from closed-form solutions of Poisson's equation, and current continuity equationExpand
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Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs
A one-dimensional (1-D) analytic solution is derived for an undoped (or lightly doped) double-gate (DG) MOSFET by incorporating only the mobile charge term in Poisson's equation. The solution isExpand
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Generalized scale length for two-dimensional effects in MOSFETs
We derive a new scale length for two-dimensional (2-D) effects in MOSFETs and discuss its significance. This derivation properly takes into account the difference in permittivity between the SiExpand
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25 nm CMOS design considerations
This paper explores the limit of bulk (or partially-depleted SOI) CMOS scaling. A feasible design for 25 nm (channel length) CMOS, without continued scaling of oxide thickness and power supplyExpand
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MOSFET channel length: extraction and interpretation
This paper focuses on MOSFET channel length: its definition, extraction, and physical interpretation. After a brief review of the objectives of channel length extraction and previous extractionExpand
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