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Memory architecture
Memory architecture describes the methods used to implement electronic computer data storage in a manner that is a combination of the fastest, most…
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30 relations
16-bit
32-bit
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Bus (computing)
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Computer memory
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
SpaceFibre network and routing switch
S. Parkes
,
A. F. Florit
,
Alberto G. Villafranca
,
C. McClements
,
D. McLaren
IEEE Aerospace Conference
2017
Corpus ID: 12464610
SpaceFibre is the next generation of the widely used SpaceWire technology for spacecraft on-board data-handling applications…
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2011
2011
Parallel SAT Solving-Using More Cores
Norbert Manthey
2011
Corpus ID: 13910959
A parallelization approach for SAT solving is presented. Common parallel portfolio approaches seem to stagnate at four parallel…
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2010
2010
Parallel Simulation of Massively Coupled Interconnect Networks
D. Paul
,
N. Nakhla
,
R. Achar
,
M. Nakhla
IEEE Transactions on Advanced Packaging
2010
Corpus ID: 40396693
In a system containing high-speed interconnects, the presence of a large number of coupled lines seriously limits the ability to…
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2009
2009
Parallel Memory Architecture for Application-Specific Instruction-Set Processors
Teemu Pitkänen
,
Jarno K. Tanskanen
,
Risto Mäkinen
,
J. Takala
Journal of Signal Processing Systems
2009
Corpus ID: 1283640
Many of the current applications used in battery powered devices are from digital signal processing, telecommunication, and…
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2009
2009
Evaluating CMPs and Their Memory Architecture
C. Jesshope
,
M. Lankamp
,
Li Zhang
ARCS
2009
Corpus ID: 1975581
Many-core processor architectures require scalable solutions that reflect the locality and power constraints of future…
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2003
2003
Processor support for temporal predictability - the SPEAR design example
Martin Delvai
,
Wolfgang Huber
,
P. Puschner
,
A. Steininger
15th Euromicro Conference on Real-Time Systems…
2003
Corpus ID: 12493430
The demand for predictable timing behavior is characteristic for real-time applications. Experience has shown that this property…
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Review
2000
Review
2000
CHIPKILL CORRECT MEMORY ARCHITECTURE
David Locklear
2000
Corpus ID: 2804813
This article reviews the chipkill correct memory architecture that is currently implemented in DellTM PowerEdgeTM 6400 and 6450…
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1995
1995
Architectural exploration for datapaths with memory hierarchy
N. D. Holmes
,
D. Gajski
Proceedings the European Design and Test…
1995
Corpus ID: 7496784
In this paper, we present a new design-space exploration algorithm, the architecture explorer (AE), for analyzing performance…
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1994
1994
Memory Architecture and Parallel Access
M. Gössel
,
B. Rebel
,
R. Creutzburg
1994
Corpus ID: 60584680
Introduction. Theory of Raster or Array Memories. Fundamental concepts and notions. Module assignment functions and conflict-free…
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1986
1986
The memory architecture and the cache and memory management unit for the fairchild clipper processor
Jeonghun Cho
,
A. Smith
,
H. Sachs
1986
Corpus ID: 59878150
The Fairchild CLIPPER is a new high-performance three chip module consisting of a microprocessor chip and two cache and memory…
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