All-associativity simulation is theoretically less efficient than forest simulation or stack simulation (a commonly used simulation algorithm), in practice it is not much slower and allows the simulation of many more caches with a single pass through an address trace.
This paper addresses algorithms for dynamically varying CPU speed and voltage in order to save energy, and refers to the approach as PACE (Processor Acceleration to Conserve Energy) since the resulting schedule increases speed as the task progresses.
This paper defines a class of compatible consistency protocols supported by the current IEEE Futurebus design, referred to as the MOESI class of protocols, which has the property that any system component can select (dynamically) any action permitted by any protocol in the class, and be assured that consistency is maintained throughout the system.
design issues. Specific aspects of cache memories tha t are investigated include: the cache fetch algorithm (demand versus prefetch), the placement and replacement algorithms, line size,…
It is found that anticipatory fetching of data can lead to significant improvements in system operation and is shown how to determine optimal block sizes.
It is found that the physical I/O traffic of a wide range of server and personal computer (PC) workloads is bursty and appears to exhibit self-similar characteristics, and there is significant potential for harnessing "free" system resources to perform background tasks such as optimization of disk block layout.
It is shown that it is possible to modify any voltage scaling algorithm to minimize energy use without affecting perceived performance and a formula to do so optimally is presented and called PACE (Processor Acceleration to Conserve Energy).