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Manycore processor
Known as:
Manycore processing unit
, Many core
, Many-core processor
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Manycore processors are specialist multi-core processors designed for a high degree of parallel processing, containing a large number of simpler…
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Related topics
Related topics
34 relations
Actor model
Asynchronous array of simple processors
Compute kernel
Computer cluster
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Broader (2)
Computer architecture
Parallel computing
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2017
Highly Cited
2017
On-Chip Communication Network for Efficient Training of Deep Convolutional Networks on Heterogeneous Manycore Systems
Wonje Choi
,
K. Duraisamy
,
+4 authors
R. Marculescu
IEEE transactions on computers
2017
Corpus ID: 4614974
Convolutional Neural Networks (CNNs) have shown a great deal of success in diverse application domains including computer vision…
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Highly Cited
2016
Highly Cited
2016
Cycle-Accurate Network on Chip Simulation with Noxim
V. Catania
,
Andrea Mineo
,
Salvatore Monteleone
,
M. Palesi
,
Davide Patti
ACM Transactions on Modeling and Computer…
2016
Corpus ID: 5594133
The on-chip communication in current Chip-MultiProcessors (CMP) and MultiProcessor-SoC (MPSoC) is mainly based on the Network-on…
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Highly Cited
2014
Highly Cited
2014
SCORPIO: A 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering
Bhavya K. Daya
,
C. Chen
,
+6 authors
L. Peh
International Symposium on Computer Architecture
2014
Corpus ID: 3684647
In the many-core era, scalable coherence and on-chip interconnects are crucial for shared memory processors. While snoopy…
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Highly Cited
2014
Highly Cited
2014
Parallel deblocking filter for HEVC on many-core processor
C. Yan
,
Yongdong Zhang
,
Feng Dai
,
Xi Wang
,
Liang Li
,
Qionghai Dai
2014
Corpus ID: 62137591
High-efficiency video coding (HEVC) is the next generation standard of video coding. The deblocking filter (DF) constitutes a…
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Highly Cited
2013
Highly Cited
2013
Silicon photonics for next generation system integration platform
Y. Arakawa
,
Takahiro Nakamura
,
Y. Urino
,
Tomoyuki Fujita
IEEE Communications Magazine
2013
Corpus ID: 14320269
New semiconductor technologies such as many-core processors and 3D memories are being researched in order to overcome the…
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Highly Cited
2011
Highly Cited
2011
DBAR: An efficient routing algorithm to support multiple concurrent applications in networks-on-chip
Sheng Ma
,
Natalie D. Enright Jerger
,
Zhiying Wang
International Symposium on Computer Architecture
2011
Corpus ID: 9586900
With the emergence of many-core architectures, it is quite likely that multiple applications will run concurrently on a system…
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Highly Cited
2010
Highly Cited
2010
Inter-block GPU communication via fast barrier synchronization
S. Xiao
,
Wu-chun Feng
IEEE International Parallel and Distributed…
2010
Corpus ID: 1494587
While GPGPU stands for general-purpose computation on graphics processing units, the lack of explicit support for inter-block…
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Review
2009
Review
2009
Cascaded Microresonator-Based Matrix Switch for Silicon On-Chip Optical Interconnection
A. Poon
,
Xianshu Luo
,
Fang Xu
,
Hui Chen
Proceedings of the IEEE
2009
Corpus ID: 22405544
This paper reviews developments in cascaded microresonator-based matrix switches for silicon photonic interconnection networks in…
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Highly Cited
2009
Highly Cited
2009
SD-VBS: The San Diego Vision Benchmark Suite
Sravanthi Kota Venkata
,
Ikkjin Ahn
,
+5 authors
M. Taylor
IEEE International Symposium on Workload…
2009
Corpus ID: 78184
In the era of multi-core, computer vision has emerged as an exciting application area which promises to continue to drive the…
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Highly Cited
2006
Highly Cited
2006
Dynamic power-performance adaptation of parallel computation on chip multiprocessors
Jian Li
,
José F. Martínez
The Twelfth International Symposium on High…
2006
Corpus ID: 12936200
Previous proposals for power-aware thread-level parallelism on chip multiprocessors (CMPs) mostly focus on multiprogrammed…
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