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MCDRAM
Multi-Channel DRAM or MCDRAM (pronounced em cee dee ram) is a 3D-stacked DRAM that is used in the Intel Xeon Phi processor codenamed Knights Landing…
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Related topics
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8 relations
Broader (3)
Computer architecture
Computer memory
Parallel computing
Dynamic random-access memory
High Bandwidth Memory
Hybrid Memory Cube
Three-dimensional integrated circuit
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2019
2019
Efficient GPU-based parallelization of solvation calculation for the blind docking problem
Hocine Saadi
,
Nadia Nouali Taboudjemat
,
Abdellatif Rahmoun
,
Baldomero Imbernón
,
H. Pérez‐Sánchez
,
J. Cecilia
Journal of Supercomputing
2019
Corpus ID: 102487627
Molecular docking techniques are widely used in computational drug discovery. Most of these techniques simulate the way that a…
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2018
2018
Multiobjective Evaluation and Optimization of CMT-bone on Intel Knights Landing
M. Gadou
,
Tania Banerjee-Mishra
,
Meenakshi Arunachalam
,
G. Shipman
,
S. Ranka
International Green and Sustainable Computing…
2018
Corpus ID: 195775193
CMT-bone is a proxy-app for simulating compressible multiphase turbulence. The application uses discretization and numerical…
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2017
2017
Power-aware computing: Measurement, control, and performance analysis for Intel Xeon Phi
A. Haidar
,
Heike Jagode
,
A. YarKhan
,
Phil Vaccaro
,
S. Tomov
,
J. Dongarra
IEEE Conference on High Performance Extreme…
2017
Corpus ID: 22176308
The emergence of power efficiency as a primary constraint in processor and system designs poses new challenges concerning power…
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2017
2017
The Open Community Runtime on the Intel Knights Landing Architecture
J. Dokulil
,
Siegfried Benkner
,
J. Yaghob
International Conference on Algorithms and…
2017
Corpus ID: 32730363
The Intel Xeon Phi Knights Landing manycore processor comes with new interesting features: on-chip high-bandwidth memory and…
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2017
2017
Enhanced memory management for scalable MPI intra-node communication on many-core processor
Joong-Yeon Cho
,
Hyun-Wook Jin
,
Dukyun Nam
EuroMPI/USA
2017
Corpus ID: 1773412
As the number of cores installed in a single computing node drastically increases, the intra-node communication between parallel…
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Review
2017
Review
2017
Multi-level spatial and temporal tiling for efficient HPC stencil computation on many-core processors with large shared caches
Charles R. Yount
,
A. Duran
,
Josh Tobin
Future generations computer systems
2017
Corpus ID: 57380369
2017
2017
Interactive Code Adaptation Tool for Modernizing Applications for Intel Knights Landing Processors
R. Arora
,
L. Koesterke
Practice and Experience in Advanced Research…
2017
Corpus ID: 1725800
The process of code adaptation to take advantage of the latest innovations in a supercomputing platform begins with learning…
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2017
2017
An Efficient Implementation of the Transitive Closure Problem on Intel KNL Architecture
I. Afanasyev
2017
Corpus ID: 53507711
An important trend in modern supercomputing is a frequent usage of co-processors, such as GPUs and Intel Xeon PHIs. The recent…
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2016
2016
Performance Optimisation of Smoothed Particle Hydrodynamics Algorithms for Multi/Many-Core Architectures
F. Baruffa
,
L. Iapichino
,
N. Hammer
,
V. Karakasis
International Symposium on High Performance…
2016
Corpus ID: 7602037
We describe a strategy for code modernisation of Gadget, a widely used community code for computational astrophysics. The focus…
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2016
2016
Estimating the Performance Impact of the MCDRAM on KNL Using Dual-Socket Ivy Bridge Nodes on Cray XC 30
Zhengji Zhao
,
M. Marsman
2016
Corpus ID: 13136452
NERSC is preparing for its next petascale system, named Cori, a Cray XC system based on the Intel KNL MIC architecture. Each Cori…
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