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MCDRAM
Multi-Channel DRAM or MCDRAM (pronounced em cee dee ram) is a 3D-stacked DRAM that is used in the Intel Xeon Phi processor codenamed Knights Landing…
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Related topics
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8 relations
Broader (3)
Computer architecture
Computer memory
Parallel computing
Dynamic random-access memory
High Bandwidth Memory
Hybrid Memory Cube
Three-dimensional integrated circuit
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2020
2020
McDRAM v2: In-Dynamic Random Access Memory Systolic Array Accelerator to Address the Large Model Problem in Deep Neural Networks on the Edge
Seunghwan Cho
,
Haerang Choi
,
Eunhyeok Park
,
Hyunsung Shin
,
S. Yoo
IEEE Access
2020
Corpus ID: 220891847
The energy efficiency of accelerating hundreds of MB-large deep neural networks (DNNs) in a mobile environment is less than that…
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2019
2019
K-Athena: A Performance Portable Structured Grid Finite Volume Magnetohydrodynamics Code
P. Grete
,
F. Glines
,
B. O’Shea
IEEE Transactions on Parallel and Distributed…
2019
Corpus ID: 152282561
Large scale simulations are a key pillar of modern research and require ever-increasing computational resources. Different novel…
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2019
2019
Efficient GPU-based parallelization of solvation calculation for the blind docking problem
Hocine Saadi
,
Nadia Nouali Taboudjemat
,
Abdellatif Rahmoun
,
Baldomero Imbernón
,
H. Pérez‐Sánchez
,
J. Cecilia
Journal of Supercomputing
2019
Corpus ID: 102487627
Molecular docking techniques are widely used in computational drug discovery. Most of these techniques simulate the way that a…
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2019
2019
Efficient Parallel Sort on AVX-512-Based Multi-Core and Many-Core Architectures
Zekun Yin
,
Tianyu Zhang
,
+4 authors
Weiguo Liu
IEEE 21st International Conference on High…
2019
Corpus ID: 203655439
Sorting kernels are a fundamental part of numerous applications. The performance of sorting implementations is usually limited by…
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2018
2018
Optimizations of Unstructured Aerodynamics Computations for Many-core Architectures
Mohammed Al Farhan
,
D. Keyes
IEEE Transactions on Parallel and Distributed…
2018
Corpus ID: 52196497
We investigate several state-of-the-practice shared-memory optimization techniques applied to key routines of an unstructured…
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2017
2017
Automating the Application Data Placement in Hybrid Memory Systems
Harald Servat
,
Antonio J. Peña
,
Germán Llort
,
Estanislao Mercadal
,
Hans-Christian Hoppe
,
Jesús Labarta
IEEE International Conference on Cluster…
2017
Corpus ID: 23871505
Multi-tiered memory systems, such as those based on Intel® Xeon Phi™processors, are equipped with several memory tiers with…
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Review
2017
Review
2017
Multi-level spatial and temporal tiling for efficient HPC stencil computation on many-core processors with large shared caches
Charles R. Yount
,
A. Duran
,
Josh Tobin
Future generations computer systems
2017
Corpus ID: 57380369
2017
2017
Power-aware computing: Measurement, control, and performance analysis for Intel Xeon Phi
A. Haidar
,
Heike Jagode
,
A. YarKhan
,
Phil Vaccaro
,
S. Tomov
,
J. Dongarra
IEEE Conference on High Performance Extreme…
2017
Corpus ID: 22176308
The emergence of power efficiency as a primary constraint in processor and system designs poses new challenges concerning power…
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2017
2017
The Open Community Runtime on the Intel Knights Landing Architecture
J. Dokulil
,
S. Benkner
,
J. Yaghob
International Conference on Algorithms and…
2017
Corpus ID: 32730363
The Intel Xeon Phi Knights Landing manycore processor comes with new interesting features: on-chip high-bandwidth memory and…
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2016
2016
Effective Use of Large High-Bandwidth Memory Caches in HPC Stencil Computation via Temporal Wave-Front Tiling
Charles R. Yount
,
A. Duran
International Workshop on Performance Modeling…
2016
Corpus ID: 14623597
Stencil computation is an important class of algorithms used in a large variety of scientific-simulation applications. The…
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