Hybrid Memory Cube

Known as: HMC, The Hybrid Memory Cube, The Hybrid Memory Cube Consortium 
Hybrid Memory Cube (HMC) is a high-performance RAM interface for through-silicon vias (TSV)-based stacked DRAM memory competing with the incompatible… (More)
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Papers overview

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2018
2018
This paper presents an evaluation of the Hybrid Memory Cube (HMC) usage in the Embedded Systems (ES) context. HMC can provide… (More)
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2017
2017
3D-stacked DRAM has been actively studied to overcome the limits of conventional DRAM. The Hybrid Memory Cube (HMC) is a type of… (More)
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2016
2016
Low-power and high-bandwidth communication can be established with TSV (through-silicon via) based Hybrid Memory Cube (HMC). This… (More)
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2015
2015
The Hybrid Memory Cube is an early commercial product embodying attributes of future stacked DRAM architectures, namely large… (More)
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2015
2015
The link between the processor and memory is one of the last remaining parallel buses and a major performance bottleneck in… (More)
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2015
2015
The Hybrid Memory Cube (HMC) is a promising alternative to DDRx memory due to its potential to achieve significantly higher… (More)
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Highly Cited
2013
Highly Cited
2013
Memory bandwidth has been one of the most critical system performance bottlenecks. As a result, the HMC (Hybrid Memory Cube) has… (More)
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2013
2013
Main memory performance is becoming an increasingly important factor contributing to overall system performance, especially due… (More)
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Highly Cited
2012
Highly Cited
2012
Multi-core processor performance is limited by memory system bandwidth. The Hybrid Memory Cube is a three-dimensional DRAM… (More)
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Highly Cited
2011
Highly Cited
2011
This article consists of a collection of slides from the author's conference presentation on the special features, system design… (More)
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