Skip to search form
Skip to main content
Skip to account menu
Semantic Scholar
Semantic Scholar's Logo
Search 218,568,885 papers from all fields of science
Search
Sign In
Create Free Account
Four-phase logic
Known as:
Four phase logic
Four-phase logic is a type of, and design methodology for, dynamic logic. It enabled non-specialist engineers to design quite complex ICs, using…
Expand
Wikipedia
(opens in a new tab)
Create Alert
Alert
Related topics
Related topics
11 relations
CMOS
Clock signal
Combinational logic
Domino logic
Expand
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2012
2012
Implementation of ALU Using Asynchronous Design
P. Amrutha
,
G. Reddy
2012
Corpus ID: 54830094
Power consumption has become one of the biggest challenges in design of high performance microprocessors. In this paper we…
Expand
2010
2010
An Asynchronous FPGA with Two-Phase Enable-Scaled Routing
Christopher LaFrieda
,
Benjamin Hill
,
R. Manohar
IEEE Symposium on Asynchronous Circuits and…
2010
Corpus ID: 2986466
The configurable routing in asynchronous FPGAs accounts for 80-90% of the total area and consumes 80-90% of the total power. This…
Expand
2001
2001
High-speed CMOS logic circuits in capacitor coupling technique
Hong-Yi Huang
,
Teng-Neng Wang
ISCAS . The IEEE International Symposium on…
2001
Corpus ID: 35770443
A pipelined four-phase logic circuit called the CMOS capacitor coupling logic (C/sup 3/L) circuit is proposed. The operation of…
Expand
1998
1998
Phased Labeled Logics of Conditional Goals
Leendert van der Torre
European Conference on Logics in Artificial…
1998
Corpus ID: 41905713
In this paper we introduce phased labeled logics of conditional goals. Labels are used to impose restrictions on the proof theory…
Expand
1998
1998
Phased Labeled Logics of Conditional
GoalsLeendert
,
W. V. der
,
TorreIRIT
1998
Corpus ID: 16165840
In this paper we introduce phased labeled logics of conditional goals. Labels are used to impose restrictions on the proof theory…
Expand
1993
1993
Analysis and design of a new race-free four-phase CMOS logic
Chung-Yu Wu
,
Kuo-Hsing Cheng
,
J. Wan
1993
Corpus ID: 54801484
A four-phase dynamic logic, called the high-speed precharge-discharge CMOS (HS-PDCMOS) logic, is proposed and analyzed. Basically…
Expand
1989
1989
Novel dynamic CMOS logic free from problems of charge sharing and clock skew
J. S. Wang
,
Chung-Yu Wu
,
M. Tsai
1989
Corpus ID: 62677014
A novel four-phase dynamic CMOS logic is proposed, analysed and chip-tested. There are two circuit configurations in the new…
Expand
1981
1981
Single-chip per channel codec with filters utilizing /spl Delta/-/spl Sigma/ modulation
T. Misawa
,
J. Iwersen
,
L. J. Loporcaro
,
J. Ruch
1981
Corpus ID: 60865556
A single-chip per channel codec with filters, fabricated using a single poly-Si NMOS technology, is discussed. In the encoder…
Expand
1974
1974
Four phase logic systems. [including integrated microcircuits]
H. Petersen
,
D. Kinell
1974
Corpus ID: 60249471
1973
1973
Complementary MOS four-phase logic circuits
H. Petersen
,
D. Kinell
1973
Corpus ID: 60003587
Technique can provide four-phase clock signal from single-phase clock and requires only one power supply voltage. This…
Expand
By clicking accept or continuing to use the site, you agree to the terms outlined in our
Privacy Policy
(opens in a new tab)
,
Terms of Service
(opens in a new tab)
, and
Dataset License
(opens in a new tab)
ACCEPT & CONTINUE