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Domino logic
Known as:
Domino (disambiguation)
Domino logic is a CMOS-based evolution of the dynamic logic techniques based on either PMOS or NMOS transistors. It allows a rail-to-rail logic swing…
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Related topics
Related topics
13 relations
Bellmac 32
CMOS
Charge sharing
Depletion-load NMOS logic
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2018
Highly Cited
2018
Convolutional neural network for bio-medical image segmentation with hardware acceleration
M. Vardhana
,
N. Arunkumar
,
Sunitha Lasrado
,
E. Abdulhay
,
G. Ramírez-González
Cognitive Systems Research
2018
Corpus ID: 43944630
Highly Cited
2012
Highly Cited
2012
Robust low leakage controlled keeper by current-comparison domino for wide fan-in gates
A. Peiravi
,
M. Asyaei
Integr.
2012
Corpus ID: 37590873
Highly Cited
2010
Highly Cited
2010
Understanding the Effect of Process Variations on the Delay of Static and Domino Logic
M. Alioto
,
G. Palumbo
,
M. Pennisi
IEEE Transactions on Very Large Scale Integration…
2010
Corpus ID: 25092838
In this paper, the effect of process variations on delay is analyzed in depth for both static and dynamic CMOS logic styles…
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2001
2001
Crosstalk noise minimization in domino logic design
Ki-Wook Kim
,
S. Kang
IEEE Trans. Comput. Aided Des. Integr. Circuits…
2001
Corpus ID: 46490262
Based on the new concept of crosstalk immunity set (CIS), procedures to minimize capacitive crosscoupling effects are developed…
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Highly Cited
1999
Highly Cited
1999
Dual threshold voltage domino logic
J. Kao
Proceedings of the 25th European Solid-State…
1999
Corpus ID: 11822613
Dual threshold voltage (DVT) domino logic utilizes dual V<inf>t</inf>'s to provide the performance equivalent of a purely low V…
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Review
1999
Review
1999
Modeling and design of asynchronous circuits
M. B. Josephs
,
S. Nowick
,
K. V. Berkel
Proceedings of the IEEE
1999
Corpus ID: 12051847
This technology review explores the behavioral and structural design domains for asynchronous circuits and systems. It proceeds…
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1998
1998
Technology mapping for domino logic
Min Zhao
,
S. Sapatnekar
IEEE/ACM International Conference on Computer…
1998
Corpus ID: 14991731
Domino logic is a popular configuration for implementing high-speed circuits. An algorithm for domino logic mapping, under a…
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Highly Cited
1997
Highly Cited
1997
Fast adders using enhanced multiple-output domino logic
Zhongde Wang
,
G. Jullien
,
W. Miller
,
Jinghong. Wang
,
S. Bizzan
IEEE J. Solid State Circuits
1997
Corpus ID: 62082173
Using an enhanced multiple output domino logic (EMODL) implementation of a carry lookahead adder (CLA), sums of several…
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Highly Cited
1989
Highly Cited
1989
Test Pattern Generation for Sequential MOS Circuits by Symbolic Fault Simulation
Kyeongsoon Cho
,
R. Bryant
26th ACM/IEEE Design Automation Conference
1989
Corpus ID: 15933879
The COSMOS symbolic fault simulator generates test sets for combinational and sequential MOS circuits represented at the switch…
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Highly Cited
1987
Highly Cited
1987
A comparison of CMOS circuit techniques: differential cascode voltage switch logic versus conventional logic
K. M. Chu
,
D. Pulfrey
1987
Corpus ID: 230534
Differential cascode voltage switch (DCVS) logic is a CMOS circuit technique that has potential advantages over conventional NAND…
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