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A CMOS charge pump for low voltage operation
TLDR
This paper proposes a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. Expand
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The Time Dilation Technique for Timing Error Tolerance
TLDR
The Time Dilation design technique is proposed that provides concurrent error detection and correction in the field of application and also supports off-line manufacturing scan testing. Expand
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A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism
TLDR
In this work, a concurrent error detection and correction circuit and technique are presented in this work. Expand
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A hierarchical architecture for concurrent soft error detection based on current sensing
TLDR
We propose a hierarchical architecture for concurrent soft error detection that provides very low area overhead, small detection times and negligible performance penalty. Expand
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Cost and power efficient timing error tolerance in flip-flop based microprocessor cores
TLDR
We present a low-cost and low-power, multiple timing error detection and correction technique, which is based on a new flip-flop design. Expand
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On the latency, energy and area of checkpointed, superscalar register alias tables
TLDR
We present two full-custom implementations of the Register Alias Table (RAT) for a 4-way superscalar dynamically-scheduled processor in a commercial 130nm CMOS technology. Expand
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A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators
TLDR
In this paper, a new Design for Testability (DFT) scheme is proposed, for the testing of LC-tank CMOS Voltage Controlled Oscillators (VCOs). Expand
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New test pattern generation units for NPSF oriented memory built-in self test
TLDR
In this paper we present the design of deterministic test pattern generation (TPG) units which can be exploited in a built-in self-test (BIST) scheme for memory type-1 NPSF testing. Expand
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High performance level restoration circuits for low-power reduced-swing interconnect schemes
TLDR
Two high performance level restoration circuits are proposed, suitable for high performance low-swing interconnect schemes. Expand
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A direct conversion receiver analysis for multistandard wireless applications
TLDR
This paper presents a direct conversion receiver modified for tri-band operation (GSM900/GSM1800/PCS1900). Expand
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