Low power dynamic logic circuit design using a pseudo dynamic buffer

@article{Tang2012LowPD,
  title={Low power dynamic logic circuit design using a pseudo dynamic buffer},
  author={Fang Tang and Amine Bermak and Zhouye Gu},
  journal={Integration},
  year={2012},
  volume={45},
  pages={395-404}
}
In this paper, we propose a pseudo dynamic buffer (PDB) for footed domino logic circuit implementation. Using the proposed PDB structure, the output pulse during the precharge process is prevented from propagating to the output stage, as is the case in conventional case. As a result, up to half of the power is saved compared to a conventional domino gate, while improving the sampling window of the dynamic gate. This PDB structure is applicable not only for Pull-down network (N-type) dynamic… CONTINUE READING