Floorplan (microelectronics)

Known as: Floor planning, Floorplan (integrated circuits), Floorplanning 
In electronic design automation, a floorplan of an integrated circuit is a schematic representation of tentative placement of its major functional… (More)
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Highly Cited
2004
Highly Cited
2004
Network-on-chip (NoC) has been proposed as a solution for the communication challenges of system-on-chip (SoC) design in the… (More)
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Highly Cited
2004
Highly Cited
2004
Increasing communication demands of processor and memory cores in Systems on Chips (SoCs) necessitate the use of Networks on Chip… (More)
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Highly Cited
2004
Highly Cited
2004
Voltage islands enable core-level power optimization for System-on-Chip (SoC) designs by utilizing a unique supply voltage for… (More)
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Highly Cited
2003
Highly Cited
2003
Classical floorplanning minimizes a linear combination of area and wirelength. When Simulated Annealing is used, e.g., with the… (More)
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Highly Cited
2001
Highly Cited
2001
 
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Highly Cited
2000
Highly Cited
2000
Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power… (More)
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Highly Cited
1999
Highly Cited
1999
We present an ordered tree, O-tree, structure to represent non-slicing floor-plans. The O-tree uses only n (2 + rig nl) bits for… (More)
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Highly Cited
1999
Highly Cited
1999
This paper studies buffer block planning for interconnect-driven floorplanning in deep submicron designs. We first introduce the… (More)
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Highly Cited
1998
Highly Cited
1998
We present a new force directed method for global placement. Besides the well-known wire length dependent forces we use… (More)
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