• Publications
  • Influence
BioRoute: A Network-Flow-Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips
tl;dr
We present the first network-flow-based routing algorithm that can concurrently route a set of noninterfering nets for the droplet routing problem on biochips. Expand
  • 102
  • 7
  • Open Access
BioRoute: a network-flow based routing algorithm for digital microfluidic biochips
tl;dr
In this paper, we present the first network-flow based routing algorithm that can concurrently route a set of non-interfering nets for the droplet routing problem on biochips. Expand
  • 66
  • 6
  • Open Access
Temporal floorplanning using the T-tree formulation
tl;dr
We present a tree-based data structure, called T-trees, to represent the temporal ordering among tasks induced by the execution of dynamically reconfigurable FPGA architectures. Expand
  • 53
  • 6
  • Open Access
Placement of digital microfluidic biochips using the T-tree formulation
tl;dr
We formulate the placement problem of digital microfluidic biochips with a tree-based topological representation, called T-tree. Expand
  • 56
  • 5
  • Open Access
A progressive-ILP based routing algorithm for cross-referencing biochips
tl;dr
We propose the first droplet routing algorithm that directly solves the problem of routing in cross-referencing biochips. Expand
  • 72
  • 4
  • Open Access
Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation
tl;dr
We formulate the placement problem of digital microfluidic biochips with a tree-based topological representation, called T-tree. Expand
  • 94
  • 3
  • Open Access
Temporal floorplanning using 3D-subTCG
tl;dr
We use a topological floorplan representation, named 3D-subTCG (3-Dimensional sub-Transitive Closure Graph) to deal with the 3-dimensional (temporal) floorplanning/placement problem, arising from dynamically reconfigurable FPGAs. Expand
  • 40
  • 3
MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs
tl;dr
We present a new multipacking-tree representation for macro placements to handle modern mixed-size designs with large macros and high chip utilization rates. Expand
  • 31
  • 3
  • Open Access
Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs
tl;dr
We propose a two-stage task scheduling methodology to reduce leakage waste due to the delay between reconfiguration and execution time of a task without sacrificing performance. Expand
  • 12
  • 2
Temporal floorplanning using the three-dimensional transitive closure subGraph
tl;dr
We use a graph-based topological floorplan representation, named 3D-subTCG (3-Dimensional Transitive Closure subGraph), to deal with the 3-dimensional (temporal) floorplanning/placement problem, arising from dynamically reconfigurable FPGAs. Expand
  • 27
  • 1
  • Open Access