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Chip-scale package
Known as:
Wafer level chip scale package
, Chip scale package
, LFCSP
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A chip scale package or chip-scale package (CSP) is a type of integrated circuit package. Originally, CSP was the acronym for chip-size packaging…
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Related topics
Related topics
9 relations
Ball grid array
Die (integrated circuit)
Embedded Wafer Level Ball Grid Array
Flip chip
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2016
2016
Development of 3D Thin WLCSP Using Vertical Via Last TSV Technology with Various Temporary Bonding Materials and Low Temperature PECVD Process
Zhiyi Xiao
,
Jun Fan
,
+4 authors
Wei Zhang
Electronic Components and Technology Conference
2016
Corpus ID: 21337583
3D WLCSP using via last TSV (through silicon via) technology is an ideal packaging technology to meet small-form-factor, high I/O…
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2013
2013
Prediction of board-level performance of WLCSP
Yumin Liu
,
Y. Liu
IEEE 63rd Electronic Components and Technology…
2013
Corpus ID: 25120069
The board level performance of both thermal cycling test and drop test is investigated to ensure good design and robust…
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2013
2013
MmW devices: from WLCSP to smart interposers
Y. Lamy
,
O. El Bouayadi
,
+9 authors
B. Fléchet
2013
Corpus ID: 117531144
2012
2012
A hybrid panel embedding process for fanout
J. Hunt
,
Kidd Lee
,
P. Shih
,
J. Lin
Electronic Packaging Technology Conference
2012
Corpus ID: 24825453
As die sizes shrink with technology node advances, the area of WLCSP dice is becoming too small to accommodate all of the solder…
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2006
2006
An optimization analysis of UBM thicknesses and solder geometry on a wafer level chip scale package using robust methods
Heng-Cheng Lin
,
C. Kung
,
Rong-Sheng Chen
,
G. Liang
2006
Corpus ID: 62803213
Wafer level chip scale package (WLCSP) has been recognized providing clear advantages over traditional wire-bond package in…
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2000
2000
A wafer-level chip scale package build up with a metal-covered polyimide post
N. Sadakata
,
Takanao Suzuki
,
Masatoshi Inaba
,
Masatoshi Inaba
,
Mutsumi Masumoto
,
Kenji Masumoto
2000
Corpus ID: 114130287
Wafer-level chip scale packaging has been intensively being developed because of its advantages such as miniaturizing, thinning…
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1999
1999
Chip-scale packaging of a gyroscope using wafer bonding
D. Sparks
,
D. Slaughter
,
+5 authors
T. Vas
1999
Corpus ID: 113991404
The chip-scale packaging of a micromachined gyroscope is discussed. The angular rate sensor requires the micropackaging of…
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1998
1998
Chip size package : The option of choice for miniaturized medical devices
M. Töpper
,
M. Schaldach
,
+9 authors
H. Reichl
1998
Corpus ID: 108492616
Especially for medical implantables applications size reduction of electronic packaging is coupled with a high functionality and…
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1995
1995
Chip scale package with metal wiring substrate
상혁 이
1995
Corpus ID: 141437760
The present invention is the size as but similar to the size of the semiconductor bare chip user is a so-called chip scale…
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1986
1986
Silicon hybrid wafer-scale package technology
R. Johnson
,
J. Davidson
,
R. Jaeger
,
D. Kerns
1986
Corpus ID: 62646357
A wafer-scale packaging technology is discussed. Pretested IC chips are mounted in holes etched through silicon wafers. Chips are…
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