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Carry-save adder
Known as:
CSA
, Carry save adder
A carry-save adder is a type of digital adder, used in computer microarchitecture to compute the sum of three or more n-bit numbers in binary. It…
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Related topics
Related topics
11 relations
Adder (electronics)
Adder–subtractor
Carry (arithmetic)
Carry-lookahead adder
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
Modified energy efficient carry save adder
Benisha Bennet
,
S. Maflin
International Conference on Circuits, Power and…
2015
Corpus ID: 17583224
The main aim of the paper is to produce the asynchronous energy efficient of the carry save adder. In the past decade, the VLSI…
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2014
2014
Efficient modulo 2n+1 multiply and multiply-add units based on modified Booth encoding
C. Efstathiou
,
N. Moschopoulos
,
N. Axelos
,
K. Pekmestzi
Integr.
2014
Corpus ID: 28057567
2013
2013
Domain-Knowledge Optimized Simulated Annealing for Network-on-Chip Application Mapping
C. Radu
,
L. Vintan
2013
Corpus ID: 59697138
Network-on-Chip architectures are scalable on-chip interconnection networks. They replace the inefficient shared buses and are…
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2010
2010
Multi-operand decimal addition by efficient reuse of a binary carry-save adder tree
Álvaro Vázquez
,
E. Antelo
Conference Record of the Forty Fourth Asilomar…
2010
Corpus ID: 23558664
We present a novel method for hardware design of combined binary/decimal multi-operand adders. More specifically, we apply this…
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2007
2007
High speed reconfigurable computation for electronic instrumentation in space applications
D. Lampridis
2007
Corpus ID: 14034462
This paper presents a new reconfigurable high-performance approach for digital pulse detection of very fast transients. The…
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2006
2006
A Low-Power Unified Arithmetic Unit for Programmable Handheld 3-D Graphics Systems
Byeong-Gyu Nam
,
Hyejung Kim
,
H. Yoo
IEEE Journal of Solid-State Circuits
2006
Corpus ID: 1910964
A low-power, area-efficient four-way 32-bit multifunction arithmetic unit has been developed for programmable shaders for…
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2005
2005
Design of a Radix-2m Hybrid Array Multiplier Using Carry Save Adder
M. Fonseca
,
E. Costa
,
S. Bampi
,
J. Monteiro
Symposium on Integrated Circuits and Systems…
2005
Corpus ID: 1283999
In this work, we present a design of a radix-2m Hybrid array multiplier using Carry Save Adder (CSA) circuit in the partial…
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2004
2004
A low latency and low power dynamic Carry Save Adder
R. Datta
,
J. Abraham
,
+5 authors
K. Nowka
IEEE International Symposium on Circuits and…
2004
Corpus ID: 6643258
This paper presents a 4-to-2 Carry Save Adder (CSA) using dynamic logic and the Limited Switch Dynamic Logic (LSDL) circuit…
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1999
1999
Bit-level arithmetic optimization for carry-save additions
Kei-Yong Khoo
,
Zhan Yu
,
A. Willson
IEEE/ACM International Conference on Computer…
1999
Corpus ID: 12668400
Addresses the bit-level optimization of carry-save adder (CSA) arrays when the operands are of unequal wordlength (such as in…
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1974
1974
Fault-Tolerant Carry-Save Adders
D. Pradhan
IEEE transactions on computers
1974
Corpus ID: 38987307
In this correspondence a design of fault-tolerant carry-save adders is presented. The design of fault-tolerant carry-save adders…
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