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Carry-lookahead adder
Known as:
Full carry look ahead adder
, Carry Look-Ahead Adder
, Full carry look-ahead
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A carry-lookahead adder (CLA) or fast adder is a type of adder used in digital logic. A carry-lookahead adder improves speed by reducing the amount…
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Related topics
Related topics
9 relations
Adder (electronics)
Adder–subtractor
CMOS
Carry operator
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Papers overview
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2011
2011
Robust Asynchronous Carry Lookahead Adders
P. Balasubramanian
2011
Corpus ID: 16350724
Novel gate level synthesis of robust asynchronous carry lookahead adders based on the notion of section carry is discussed in…
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Highly Cited
2010
Highly Cited
2010
Design of High-speed Modified Booth Multipliers Operating at GHz Ranges
Soojin Kim
,
Kyeongsoon Cho
2010
Corpus ID: 17071803
— This paper describes the pipeline architecture of high-speed modified Booth multipliers. The proposed multiplier circuits are…
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2009
2009
A New Mixed Gate Diffusion Input Full Adder Topology for High Speed Low Power Digital Circuits
Adarsh Agrawal
,
Subodh Wairya
,
Sudarshan Tiwari
2009
Corpus ID: 17246526
This paper mainly presents Mixed Gate Diffusion Input Full Adder based on static CMOS inverter topology. In this proposed mixed…
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2009
2009
A Novel Power Delay Optimized 32-bit Parallel Prefix Adder For High Speed Computing
P. Ramanathan
,
P. Vanathi
2009
Corpus ID: 10710215
Parallel Prefix addition is a technique for improving the speed of binary addition. Due to continuing integrating intensity and…
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2009
2009
An improved 32-bit carry-lookahead adder with Conditional Carry-Selection
Ping Chen
,
Juan Zhao
,
Guo-bo Xie
,
Yi-jun Li
International Conference on Crowd Science and…
2009
Corpus ID: 1225092
An improved 32-bit carry-lookahead adder (CLA) with Conditional Carry-Selection (CSS) is proposed in this paper. The new adder is…
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2004
2004
Enhanced 32-bit carry look-ahead adder using multiple output enable-disable CMOS differential logic
Mário C. B. Osorio
,
Carlos A. Sampaio
,
A. Reis
,
R. Ribas
Proceedings. SBCCI . 17th Symposium on Integrated…
2004
Corpus ID: 13972675
This paper presents an enhanced 32-bit carry look-ahead (CLA) adder implemented using the multi-output enable/disable CMOS…
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2004
2004
Power Estimation of High Speed Bit-Parallel Adders
Anders Åslund
2004
Corpus ID: 107295377
Fast addition is essential in many DSP algorithms. Various structures have been introduced to speed up the time critical carry…
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2001
2001
A new code-disjoint sum-bit duplicated carry look-ahead adder for parity codes
V. Ocheretnij
,
E. Sogomonyan
,
M. Gössel
Proceedings of the Asian Test Symposium
2001
Corpus ID: 11139081
A new code-disjoint self-checking carry look-ahead adder is proposed. To reduce the necessary area and the power dissipation only…
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1997
1997
Delay-insensitive carry-lookahead adders
Fu-Chiung Cheng
,
S. Unger
,
Michael Theobald
,
Wen-Chung Cho
Proceedings Tenth International Conference on…
1997
Corpus ID: 14195182
Integer addition is one of the mast important operations in digital computer systems because the performance of processors is…
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1990
1990
Optimization and Speed Improvement Analysis of Carry-Lookahead Adder Structure
B. D. Lee
,
V. Oklobdzija
Conference Record Twenty-Fourth Asilomar…
1990
Corpus ID: 61897245
The delay characteristics of carrylookahead (CLA) adders are examined with respect to a delay model that accounts for fan-in and…
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