# Booth's multiplication algorithm

## Papers overview

Semantic Scholar uses AI to extract papers important to this topic.

Review

2017

Review

2017

- JETC
- 2017

Often as the most important arithmetic modules in a processor, adders, multipliers, and dividers determine the performance and… (More)

Is this relevant?

Highly Cited

2015

Highly Cited

2015

- 2015

Bit is added to the left of the partial product using sign extension.products required to half that required by a simple add and… (More)

Is this relevant?

Highly Cited

2011

Highly Cited

2011

- IEEE Transactions on Very Large Scale Integration…
- 2011

The fixed-width multiplier is attractive to many multimedia and digital signal processing systems which are desirable to maintain… (More)

Is this relevant?

2011

2011

- 2011

A new architecture, namely, Multiplier-andaccumulator (MAC) based Radix-4 Booth Multiplication Algorithm for high-speed… (More)

Is this relevant?

Highly Cited

2010

Highly Cited

2010

A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm

- IEEE Transactions on Very Large Scale Integration…
- 2010

In this paper, we proposed a new architecture of multiplier-and-accumulator (MAC) for high-speed arithmetic. By combining… (More)

Is this relevant?

2005

2005

- 2005

The main back-bone operation in elliptic curve cryptosystems is scalar point multiplication. The most frequently used method… (More)

Is this relevant?

2004

2004

- 10th International Symposium on Asynchronous…
- 2004

One of the main reasons for using asynchronous design is that it offers the opportunity to exploit the data-dependent latency of… (More)

Is this relevant?

Highly Cited

2004

Highly Cited

2004

- IEEE Transactions on Very Large Scale Integration…
- 2004

This paper presents an error compensation method for a modified Booth fixed-width multiplier that receives a W-bit input and… (More)

Is this relevant?

Highly Cited

2000

Highly Cited

2000

- IEEE Trans. Computers
- 2000

ÐThis paper presents a design methodology for high-speed Booth encoded parallel multiplier. For partial product generation, we… (More)

Is this relevant?

Highly Cited

1999

Highly Cited

1999

- IEEE Symposium on Computer Arithmetic
- 1999

New VLSI circuit architectures for addition and multiplication modulo(2 1) and(2 + 1) are proposed that allow the implementation… (More)

Is this relevant?