# E. Swartzlander

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- Publications
- Influence

Adder and Multiplier Design in Quantum-Dot Cellular Automata

- Heumpil Cho, E. Swartzlander
- Computer Science
- IEEE Transactions on Computers
- 1 June 2009

Quantum-dot cellular automata (QCA) is an emerging nanotechnology, with the potential for faster speed, smaller size, and lower power consumption than transistor-based technology. Quantum-dot… Expand

The Sign/Logarithm Number System

- E. Swartzlander, Aristides G. Alexopoulos
- Mathematics, Computer Science
- IEEE Transactions on Computers
- 1 December 1975

A signed logarithmic number system, which is capable of representing negative as well as positive numbers is described. A number is represented in the sign/logarithm number system by a sign bit and… Expand

Truncated multiplication with correction constant [for DSP]

- M. Schulte, E. Swartzlander
- Mathematics
- Proceedings of IEEE Workshop on VLSI Signal…
- 20 October 1993

Multiplication is frequently required in digital signal processing. Parallel multipliers provide a high-speed method for multiplication, but require large area for VLSI implementations. In most… Expand

Hybrid CORDIC Algorithms

- S. Wang, V. Piuri, E. Swartzlander
- Computer Science
- IEEE Trans. Computers
- 1 November 1997

Each coordinate rotation digital computer iteration selects the rotation direction by analyzing the results of the previous iteration. In this paper, we introduce two arctangent radices and show that… Expand

FFT Implementation with Fused Floating-Point Operations

- E. Swartzlander, H. Saleh
- Computer Science
- IEEE Transactions on Computers
- 1 February 2012

This paper describes two fused floating-point operations and applies them to the implementation of fast Fourier transform (FFT) processors. The fused operations are a two-term dot product and an… Expand

A Reduced Complexity Wallace Multiplier Reduction

- Ron S. Waters, E. Swartzlander
- Computer Science
- IEEE Transactions on Computers
- 1 August 2010

Wallace high-speed multipliers use full adders and half adders in their reduction phase. Half adders do not reduce the number of partial product bits. Therefore, minimizing the number of half adders… Expand

Hardware Designs for Exactly Rounded Elemantary Functions

- M. Schulte, E. Swartzlander
- Mathematics, Computer Science
- IEEE Trans. Computers
- 1 August 1994

This paper presents hardware designs that produce exactly rounded results for the functions of reciprocal, square-root, 2/sup x/, and log/sub 2/(x). These designs use polynomial approximation in… Expand

A Spanning Tree Carry Lookahead Adder

- T. W. Lynch, E. Swartzlander
- Computer Science
- IEEE Trans. Computers
- 1 August 1992

The design of the 56-b significant adder used in the Advanced Micro Devices Am29050 microprocessor is described. Originally implemented in a 1- mu m design role CMOS process, it evaluates 56-b sums… Expand

A First Step Toward Cost Functions for Quantum-Dot Cellular Automata Designs

- W. Liu, L. Lu, M. O'Neill, E. Swartzlander
- Physics
- IEEE Transactions on Nanotechnology
- 1 May 2014

Quantum-dot cellular automata (QCA) is potentially a very attractive alternative to CMOS for future digital designs. Circuit designs in QCA have been extensively studied. However, how to properly… Expand