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Binary multiplier
Known as:
Multiplication ALU
, Multiplier
, Hardware multiply
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A binary multiplier is an electronic circuit used in digital electronics, such as a computer, to multiply two binary numbers. It is built using…
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Related topics
Related topics
31 relations
36-bit
Ancient Egyptian multiplication
Approximate computing
Arithmetic logic unit
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2013
2013
Log-likelihood ratio algorithm for rate compatible modulation
W. Rao
,
Yan Dong
,
Fang Lu
,
Shu Wang
International Symposium on Circuits and Systems
2013
Corpus ID: 23505960
Seamless Rate Adaptation(SRA) based on rate compatible modulation(RCM) is a new receiver rate adaptive method, in which a block…
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2008
2008
The Realization of FFT Algorithm Based on FPGA Co-Processor
H. He
,
Huiqing Guo
Second International Symposium on Intelligent…
2008
Corpus ID: 9916849
The fast Fourier transform (FFT)is a computationally intensive digital signal processing(DSP)function widely used in applications…
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2004
2004
Data wordlength reduction for low-power signal processing software
Kyungtae Han
,
Brian L. Evans
,
E. Swartzlander
IEEE Workshop onSignal Processing Systems, . SIPS…
2004
Corpus ID: 3830406
Reducing power consumption prolongs battery life and increases integration. In digital CMOS designs, switching activity is…
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2004
2004
Digital FIR Filter Design Using the MSP430F16x
Murugavel Raju
2004
Corpus ID: 15563855
This application report describes an FIR filter implementation using the MSP430F16x and the MSP430F161x family devices. The…
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2004
2004
Implementing FFT in an FPGA Co-Processor
Sheac Yee Lim
,
A. Crosland
2004
Corpus ID: 14513529
The Fast Fourier Transform (FFT) is a computationally intensive digital signal processing (DSP) function widely used in…
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1999
1999
VLSI improvements in a binary multiplier based on analog digits
A. Saed
,
M. Ahmadi
,
G. Jullien
Conference Record of the Thirty-Third Asilomar…
1999
Corpus ID: 24955665
The overlap resolution number system (ORNS) employs digit level residue arithmetic with analog digits. A binary multiplier based…
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Highly Cited
1985
Highly Cited
1985
Realization of Finite Impulse Response Filters Using Coefficients +1, 0, and -1
N. Benvenuto
,
L. Franks
,
F. Hill
IEEE Transactions on Communications
1985
Corpus ID: 28193642
New classes of nonrecursive linear digital filters are proposed as alternatives to conventional methods for digital signal…
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Highly Cited
1984
Highly Cited
1984
A Wideband Sampling Wattmeter1
G. Stenbakken
IEEE Transactions on Power Apparatus and Systems
1984
Corpus ID: 36417063
The design and operation of a wideband sampling wattmeter capable of measuring distorted power signals with fundamental…
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1982
1982
A high-speed LSI GaAs 8x8 bit parallel multiplier
F. S. Lee
,
G. Kaelin
,
+6 authors
R. Eden
IEEE Journal of Solid-State Circuits
1982
Corpus ID: 22371267
Multiplication is frequently the speed-limiting function in digital signal processing systems. High-speed hardware multiplier ICs…
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1981
1981
A single-chip digital signal processor for telecommunication applications
T. Nishitani
,
R. Maruta
,
Y. Kawakami
,
H. Goto
IEEE Journal of Solid-State Circuits
1981
Corpus ID: 1894615
A single-chip, software-programmable digital signal processor, intended for telecommunication applications, has been developed…
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