A binary multiplier is an electronic circuit used in digital electronics, such as a computer, to multiply two binary numbers. It is built usingâ€¦Â (More)

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2013

2013

- Sonal Jain, Monika Kapoor, +13 authors Borivoje Nikolic
- 2013

Due to high complexity of VLSI systems used in various applications power dissipation becomes a limiting factor in VLSI circuitsâ€¦Â (More)

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2012

2012

For higher order multiplications, a huge number of adders or compressors are to be used to perform the partial product additionâ€¦Â (More)

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2011

2011

- Ismo HÃ¤nninen, Jarmo Takala, Craig S. Lent
- 2011 IEEE International Symposium of Circuits andâ€¦
- 2011

Nanocircuits will suffer from heat dissipation due to irreversible information erasure, which is a potential new limiting factorâ€¦Â (More)

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2009

2009

- Charles Tsen, Sonia Gonzalez-Navarro, Michael J. Schulte, Brian J. Hickmann, Katherine Compton
- 2009 20th IEEE International Conference onâ€¦
- 2009

In this paper, we describe the first hardware design of a combined binary and decimal floating-point multiplier, based onâ€¦Â (More)

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2004

2004

- Guojun Wang
- Conference Record of the Thirty-Eighth Asilomarâ€¦
- 2004

Multiplication is a very important operation in digital computing systems. Both signed and unsigned multiplications are requiredâ€¦Â (More)

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2004

2004

- Chip Hong Chang, Yajuan He, Jiangmin Gu
- The 2004 IEEE Asia-Pacific Conference on Circuitsâ€¦
- 2004

This work addresses the feasibility of re-engineering the multiplier architecture that is based on a new redundant numberâ€¦Â (More)

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1999

1999

- Abdullah A. Saed, M. Ahmadi, G. A. Jullien
- Conference Record of the Thirty-Third Asilomarâ€¦
- 1999

The overlap resolution number system (ORNS) employs digit level residue arithmetic with analog digits. A binary multiplier basedâ€¦Â (More)

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1998

1998

- Abdullah A. Saed, M. Ahmadi, G. A. Jullien
- Conference Record of Thirty-Second Asilomarâ€¦
- 1998

The overlap resolution number system (ORNS) employs bit level residue arithmetic, and opens up a powerful approach to digitalâ€¦Â (More)

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1988

1988

- Michitaka Kameyama, Shoji Kawahito, Tatsuo Higuchi
- Computer
- 1988

A description is given of a 32*32-bit signed digit multiplier implemented with multiple-valued, bidirectional, current-modeâ€¦Â (More)

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1985

1985

- R. Gnanasekaran
- IEEE Transactions on Computers
- 1985

A fast serial-parallel (FSP) multiplier design is derived from the carry-save add-shift (CSAS) multiplier structure. The CSASâ€¦Â (More)

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