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36-bit

Known as: 36-bit word length 
In computer architecture, 36-bit integers, memory addresses, or other data units are those that are at most 36 bits (six six-bit characters) wide… Expand
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Related topics

Related topics

40 relations
3 GB barrierAddressing modeBinary multiplierBinary-coded decimal
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Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
Directly Printable Frequency Signatured Chipless RFID Tag for IoT Applications
This paper proposes a low-cost, compact, flexible passive chipless RFID tag that has been designed and analyzed. The tag is a… Expand
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2015
2015
Pursuance of 36-bit RISC processors in collaboration with application of DSP using FPGA
Abstract—RISC has become main stream in scientific and engineering applications. The demand for (DSP) has increased with advent… Expand
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2010
2010
Investigation of properties of 36-bit adders for creation of DSP blocks on FPGA
In this paper 36-bit ripple-carry, carry-skip, carry-select and carry-lookahead adders intended for using in field programmable… Expand
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Highly Cited
2006
Highly Cited
2006
Fast packet classification using bloom filters
Ternary content addressable memory (TCAM), although widely used for general packet classification, is an expensive and high power… Expand
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2005
2005
SHD movie distribution system using image container with 4096/spl times/2160 pixel resolution and 36 bit color
The super-high-definition (SHD) movie distribution system described in this paper can transmit and display exceptionally high… Expand
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2003
2003
Virtual Memory Constraints in 32-bit Windows
Many server workloads can exhaust the 32-bit virtual address space in the Windows server operating systems. Machines configured… Expand
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1999
1999
A 36-bit balanced moduli MAC architecture
Recently a renewed interest is seen in RNS (Residue Number System) which stems out from the fact that these systems are… Expand
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1998
1998
A low-power 16-bit multiplier-accumulator using series-regulated mixed swing techniques
This paper describes an on-chip series-regulated mixed swing methodology with sleep-mode control for lowering the power… Expand
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1994
1994
A Message-driven Programming System for Fine-grain Multicomputers
This paper describes an experimental message-driven programming system for fine-grain multicomputers. The initial target… Expand
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1989
1989
J-machine: A fine-grain concurrent computer
The J-Machine is a fine-grain concurrent computer that provides low-overhead primitive mechanisms for communication… Expand
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