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36-bit
Known as:
36-bit word length
In computer architecture, 36-bit integers, memory addresses, or other data units are those that are at most 36 bits (six six-bit characters) wide…
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Related topics
Related topics
40 relations
3 GB barrier
Addressing mode
Binary multiplier
Binary-coded decimal
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
Purpose of Low-Power Linear Feedback Shift Register ( LFSR ) by using Bipartite and Random Injection Method for Low Power BIST
D. Haribabu
,
J. Ravikumar
,
C. R. Reddy
2015
Corpus ID: 85526548
In a bit of electronic systems that was practiced in safety critical application circuit testing has to be done periodically. For…
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2015
2015
Pursuance of 36-bit RISC processors in collaboration with application of DSP using FPGA
M. Manjushree
,
Savita S Patil
2015
Corpus ID: 59020217
Abstract—RISC has become main stream in scientific and engineering applications. The demand for (DSP) has increased with advent…
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2013
2013
Power Aware BIST for Digital IC ’ s Ms
Anupam Rajendran
,
P. S. Pandey
2013
Corpus ID: 12287452
Testing of digital VLSI circuits encounters many challenges as a result of rapidly growing semiconductor manufacturing…
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Review
2012
Review
2012
A parallel processing framework for spectral based computations
Andrew van der Byl
2012
Corpus ID: 60268192
Over the past 40 years, the computing industry has benefited from persistent growth largely attributed to improvements in…
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2004
2004
Handel-C implementation of classical component labelling algorithm
M. Jablonski
,
M. Gorgon
Euromicro Symposium on Digital System Design…
2004
Corpus ID: 17851157
In the paper the implementation of classical label component algorithm in Handel-C language has been discussed. The…
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2003
2003
Virtual Memory Constraints in 32-bit Windows: an Update
M. Friedman
Int. CMG Conference
2003
Corpus ID: 35699646
This paper discusses the signs that indicate a machine is suffering from a virtual memory constraint in 32-bit Windows. Machines…
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1998
1998
A low-power 16-bit multiplier-accumulator using series-regulated mixed swing techniques
R. Krishnamurthy
,
H. Schmit
,
L. Carley
Proceedings of the IEEE Custom Integrated…
1998
Corpus ID: 7048730
This paper describes an on-chip series-regulated mixed swing methodology with sleep-mode control for lowering the power…
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1998
1998
4.0 16*16+36-bit Mac Manufacturability 5.0 Conclusions
1998
Corpus ID: 17731269
at lower swings to offer improved energy/opera-tion savings. The savings increase even further with process scaling beyond our…
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1981
1981
Digital signal processor: Architecture and performance
J. Boddie
,
G. Daryanani
,
I. Eldumiati
,
R. Gadenz
,
J. Thompson
,
S. Walters
Bell Labs technical journal
1981
Corpus ID: 44218694
This paper describes the DSP, a recently developed integrated circuit implementing a programmable digital signal processor. The…
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1968
1968
Speech recognition using autocorrelation analysis
R. Purton
1968
Corpus ID: 62653817
Experiments are described in which word recognition is based on digital autocorrelation analysis followed by computer pattern…
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