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PipeRench: A Reconfigurable Architecture and Compiler
TLDR
The authors describe the PipeRench architecture and how it solves some of the pre-existing problems with FPGA architectures, such as logic granularity, configuration time, forward compatibility, hard constraints and compilation time. Expand
PipeRench: a co/processor for streaming multimedia acceleration
TLDR
A novel reconfigurable fabric architecture, PipeRench, optimized to accelerate these types of computations, which enables fast, robust compilers, supports forward compatibility, and virtualizes configurations, thus removing the fixed size constraint present in other fabrics. Expand
PipeRench: A virtualized programmable datapath in 0.18 micron technology
PipeRench is a programmable datapath that can be used to accelerate numerically intensive applications. The unique aspect of PipeRench is its ability to virtualize hardware through self-managedExpand
PipeRench: a coprocessor for streaming multimedia acceleration
Future computing workloads will emphasize an architecture's ability to perform relatively simple calculations on massive quantities of mixed-width data. This paper describes a novel reconfigurableExpand
Exploring regular fabrics to optimize the performance-cost trade-off
TLDR
Some of the trade-offs to consider for determination of how much regularity a particular IC or application can afford are discussed, and a Via Patterned Gate Array is proposed as one such example. Expand
An architectural exploration of via patterned gate arrays
In this work we investigate the architecture of a Via Patterned Gate Array (VPGA) [1], focusing primarily on: 1) the optimal lookup table (LUT) size; and 2) a comparison the crossbar and switch blockExpand
A Model and Methodology for Hardware-Software Codesign
A behavioral model of a class of mixed hardware-software systems is presented. A codesign methodology for such systems is defined. The methodology includes hardware-software partitioning, behavioralExpand
Implementation of near Shannon limit error-correcting codes using reconfigurable hardware
TLDR
This paper presents an overview of these coding schemes, then discusses the issues involved in building an LDPC decoder using reconfigurable hardware, and presents a hypothetical LDPC implementation using a commercial FPGA, which will give an idea of future research issues and performance gains. Expand
Synthesis of application-specific memory designs
TLDR
This paper introduces a novel approach to the design of memory systems, which is based on a variety of array grouping techniques and dimensional transformations, and the binding of array groups to memory components with different dimensions, access times, and number of ports. Expand
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